Timing optimization by an improved redundancy addition and removal technique

In this work a generalization of the structural Redundancy Addition and Removal (RAR) logic optimization method is presented. New concepts based on the functional description of the nodes in the network are introduced to support this generalization. Necessary and sufficient conditions to identify all the possible structural expansions are given for the general case of multiple variable expansion. Basic nodes are no longer restricted to simple gates and can be any function of any size. With this generalization, an incremental mechanism to perform structural transformations involving any number of variables can be applied in a very efficient manner. Experimental results are presented that illustrate the efficiency of our scheme.

The paper attempts to determine the capabilities of existing redundancy addition and removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the retiming and resynthesis (RaR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove the higher potential of the sequential redundancy addition and removal over the retiming and resynthesis techniques.

Redundancy Addition and Removal (RAR) and ATPG/Diagnosis-based Design Rewiring (ADDR) are both logic restructuring techniques used in the synthesis and optimization of logic designs. However, not every irredundant target wire can be successfully removed due to some limitations in these two approaches. Therefore, this paper proposes an efficient restructuring technique, Error Injection & Correction (EIC), which formally constructs a corresponding rectification network at feasible locations without verification efforts for the injected errors of the wire removal, addition, or gate replacement. We use the EIC to serve as a logic perturbation engine and combine other logic optimization engines to optimize the circuit. The experimental results show that the size of highly optimized circuits can be further reduced with this EIC technique as compared with the configuration using only logic optimization engines.

This paper presents an automatic test pattern generation (ATPG) technique applicable to register transfer level (RTL) datapath circuits which are usually very hard-to-test due to the presence of complex loop structures. Although to achieve high fault coverage it is essential to symbolically simulate all possible execution paths, we have come up with a case splitting mechanism which makes use of path sensitization information from the faulty location to primary outputs so that the size of formulae to be solved is significantly reduced. Experimental results show robustness and reliability of our method compared to the state-of-the-art RTL ATPG techniques. In addition, the results indicate that, in comparison with [8], with case splitting the ATPG time has been reduced by 22%-41%.

This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits can be performed with a modified combinational automatic test pattern generator (ATPG), which is much faster than a sequential ATPG. A combinational model is obtained by replacing all flipflops by buffers. It is shown that a test vector for a fault in this model obtained by a combinational test generator can be expanded into a sequence of identical vectors to detect the same fault in the original sequential circuit. This technique may abort a few faults which can then be resolved with a sequential ATPG. Experiments on the ISCAS89 circuits show that only 30% to 70% of flipflops require scanning in larger circuits and 96% to 100% fault coverage for almost all the circuits without resorting to a sequential ATPG.

In this paper, we propose a layout driven synthesis approach for Field Programmable Gate Arrays (FPGAs). The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA. The alternative wires (in the logic level) that can be routed through less congested areas substitute the unroutable wires without changing the circuit's functionality. Allowing the logic blocks to have alternative functions also increases the flexibility of routing. The redundancy addition and removal techniques are used to identify such alternative wires. Experimental results are presented to demonstrate the usefulness of this approach. For a set of randomly selected benchmark circuits, on the average, 30%-50% of wires have alternative wires. These results indicate that the routing flexibility can be substantially increased by considering these alternative wires. Our prototype system successfully completed the routing for two AT&T designs that cannot be handled by an FPGA router alone. The proposed synthesis technique can also be applied to standard cell and gate array designs to reduce the routing area.

Justification of multiple circuit lines in automatic test pattern generation (ATPG) is exponential in complexity in the presence of reconvergent fanout. Reconvergent fanout consequently is a chief source of increased complexity in the ATPG process. Reconvergence also degrades the pseudo-random test by producing correlation between inputs of the same combinational logic block. Consideration of reconvergence during synthesis can result in its elimination at minimal area or performance cost. The high regularity of DSP architectures facilitates reconvergence reduction, when, it is addressed during synthesis. We present a design-for-testability approach to remove reconvergence during high-level synthesis. We have developed a method for estimating the degree of reconvergence, based on an estimate of the existence of paths between each pair of hardware units. We have designed and implemented scheduling and binding algorithms which use the proposed reconvergence estimate to consistently direct synthesis to RTL datapaths with reduced reconvergent fanout. The experimental results shown demonstrate the effectiveness of the proposed methodology.

Today, VLSI design has progressed to a stage where it needs to incorporate methods of testing circuits. The Automatic Test Pattern Generation (ATPG) is a very attractive method and feasible on almost any combinational and sequential circuit. Currently available automatic test pattern generators (ATPGs) generate test sets that may be excessively long. Because a cost of testing depends on the test length, compaction techniques have been used to reduce that length. The motivation for studying test compaction is twofold. Firstly, by reducing the test sequence length, the memory requirements during the test application and the test application time are reduced. Secondly, the extent of test compaction possible for deterministic test sequences indicates that test pattern generators spend a significant amount of time generating test vectors that are not necessary. The compacted test sequences provide a target for more efficient deterministic test generators. Two types of compaction techniques exist: dynamic and static. The dynamic test sequence compaction performs compaction concurrently with the test generation process and often requires modification of the test generator. The static test sequence compaction is done in a post-processing step to the test generation and is independent of the test generation algorithm and process. In the thesis, a new idea for static compaction of test sequences for synchronous sequential circuits has been proposed. Our new method - SUSEM (Set Up Sequence Elimination Method) uses the circuit state information to eliminate some setup sequences for the target faults and consequently reduce the test sequence length. The technique has been used for the test sequences generated by HITEC test generator. ISCAS89 benchmark circuits were used in our experiments, for some circuits which have a large number of target faults and relatively small number of flip-flops, the very significant compactions have been obtained. The more important is that this method can be used to improve the test generation procedure unlike most static compaction methods which blindly or randomly remove parts of test vectors and cannot be used to improve the test generators.

Testing the K longest paths through each gate (KLPG) in a circuit detects the smallest local delay faults under process variation. In this work a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate in a combinational circuit is presented. Many techniques are used to significantly reduce the search space. The results on the ISCAS benchmark circuits show that this methodology is very efficient and able to handle circuits with an exponential number of paths, such as c6288.

The timing optimization of multiphase logic entails the reduction of the overall cycle time of the machine and/or input-to-output delays by distributing computation throughout the entire clock cycle. A tool has been developed to automatically perform this optimization task, and it has been implemented as a set of extensions to the combinational logic optimization tool, misII. The algorithms yield improvements that are on average 10-20% better than what is achievable using purely combinational logic optimization tools that do not move logic across latches. These improvements represent 75% of what would be possible in the most idealized case. Results on simple two-phase circuits show average input-to-output delay improvements of 13% with area penalties of 11%. For a four-phase controller used in the SPUR processor it yields an improvement in cycle time of 18% with an area penalty of 11%. Experiments indicate that the optimization algorithm is highly insensitive to parameter variations in the underlying combinational logic optimization routines and initial state assignment. >

Redundancy addition and removal, also known as rewiring, is a building block of a wide range of circuit optimization applications. In this paper, we propose a novel improvement on the FIRE redundancy identification technique and augment the state-of-the-art rewiring scheme RAMFIRE with it. Our method increases the number of alternative wires identified by 10% and improves the runtime by nearly 20%. Optimization applications based on rewiring can take the advantage of this speed up and enhanced rewiring power.

Representing finite state systems by means of finite state machines is a common approach in VLSI circuit design. BDD-based algorithms have made possible the manipulation of FSMs with very large state spaces; however, when the representation of the set of reachable states grows too much, the original FSM is no longer manageable as a whole, and it needs to be decomposed into smaller sub-machines. Structural analysis of the circuit from which the FSM has been extracted has shown to be very effective to determine good state variable partitions which induce FSM decomposition for logic synthesis and formal verification applications. In this paper we propose FSM analysis techniques based on connectivity and spectral characteristics of the state machine which take into account the mutual dependency of the state variables, but which are no longer dependent on the structure of the underlying circuit; therefore, they may be used in a context different from sequential logic optimization and FSM verification.

DFT (Design for Testability) is a methodology of testing for manufacturing defects in a chip. DFT consists of scan, ATPG (Automatic test pattern generation) methodologies and the BIST (Built in self-test) methods. This paper explores ATPG for pattern generation and LBIST (Logic built-in self-test) for testing. LBIST is explored and tested using pseudorandom test pattern generation. The fault list created for undetected faults are dumped into ATPG and fault specific test patterns are generated. These patterns detect the random pattern resistant faults (which are undetected by pseudorandom testing patterns). Further, a smart compression algorithm is defined to compress the pattern which can be stored inside the chip for LBIST testing, with no added memory overhead, and the minimum extra hardware (which only comprises of combinational logic). The proposed algorithm has been reviewed and analyzed and it has been found that the fault coverage achieved is 86.01%.

In this paper, a new approach for generating test vectors that detects faults in combinational circuits is introduced. The approach is based on automatically designing a circuit which implements the D-algorithm, an automatic test pattern generation (ATPG) algorithm, specialized for the combinational circuit. Our approach exploits fine-grain parallelism by performing the following in three clock cycles: direct backward/forward implications, conflict checking, selecting next gate to propagate fault or to justify a line, decisions on gate inputs, loading the state of the circuit after backup. In this paper, we show the feasibility of this approach in terms of speed, and how it compares with software based techniques.

Necessary, nonconflicting, and arbitrary assignments can be distinguished during algorithmic test pattern generation. The identification of necessary and nonconflicting assignments is algorithmic in the sense that there is no element of choice or luck in the computation, no reliance on heuristics, and no possibility of these assignments causing a backtrack if the fault is testable. This paper presents algorithms based on the mathematical properties of images and inverse images of set functions to define reduction and tendency lists in combinational logic circuits, used to identify necessary and nonconflicting assignments, respectively. Issues relating to the efficient implementation of these algorithms are addressed from both a theoretical and practical perspective. Experimental results obtained on a variety of benchmark circuits show that algorithmic assignment identification can be used to reduce or eliminate backtracking in automatic test pattern generation. >