Improving Single-Pass Redundancy Addition and Removal with Inconsistent Assignments

The paper attempts to determine the capabilities of existing redundancy addition and removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the retiming and resynthesis (RaR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove the higher potential of the sequential redundancy addition and removal over the retiming and resynthesis techniques.

In this paper, we propose a layout driven synthesis approach for Field Programmable Gate Arrays (FPGAs). The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA. The alternative wires (in the logic level) that can be routed through less congested areas substitute the unroutable wires without changing the circuit's functionality. Allowing the logic blocks to have alternative functions also increases the flexibility of routing. The redundancy addition and removal techniques are used to identify such alternative wires. Experimental results are presented to demonstrate the usefulness of this approach. For a set of randomly selected benchmark circuits, on the average, 30%-50% of wires have alternative wires. These results indicate that the routing flexibility can be substantially increased by considering these alternative wires. Our prototype system successfully completed the routing for two AT&T designs that cannot be handled by an FPGA router alone. The proposed synthesis technique can also be applied to standard cell and gate array designs to reduce the routing area.

In this work a generalization of the structural Redundancy Addition and Removal (RAR) logic optimization method is presented. New concepts based on the functional description of the nodes in the network are introduced to support this generalization. Necessary and sufficient conditions to identify all the possible structural expansions are given for the general case of multiple variable expansion. Basic nodes are no longer restricted to simple gates and can be any function of any size. With this generalization, an incremental mechanism to perform structural transformations involving any number of variables can be applied in a very efficient manner. Experimental results are presented that illustrate the efficiency of our scheme.

Redundancy addition and removal (RAR) uses automatic test pattern generation (ATPG) techniques to identify logic optimization transforms. It has been applied successfully to combinational and sequential logic optimization and to layout driven logic synthesis for FPGAs. We present an improved RAR technique that allows to one to identify new types of optimization transforms and it is more efficient because it reduces the number of ATPG runs required. Also, we apply the RAR method to timing optimization. The experimental results show that this improved RAR technique produces significant timing optimization with very little area cost.

Redundancy Addition and Removal (RAR) and ATPG/Diagnosis-based Design Rewiring (ADDR) are both logic restructuring techniques used in the synthesis and optimization of logic designs. However, not every irredundant target wire can be successfully removed due to some limitations in these two approaches. Therefore, this paper proposes an efficient restructuring technique, Error Injection & Correction (EIC), which formally constructs a corresponding rectification network at feasible locations without verification efforts for the injected errors of the wire removal, addition, or gate replacement. We use the EIC to serve as a logic perturbation engine and combine other logic optimization engines to optimize the circuit. The experimental results show that the size of highly optimized circuits can be further reduced with this EIC technique as compared with the configuration using only logic optimization engines.

The knowledge of the state transition graph (STG) of a sequential circuit helps in generating test sequences and identifying redundancies. The application of algorithms to the identification and removal of redundancies is reported. This strategy is based on traversing the STG of the given circuit and then performing redundancy identification using the reachability information calculated by the traversal. This method considers one candidate redundancy at a time, in an order that tries to minimize the total processing time. Substantial area and delay reductions are achieved. Experiments show that for many circuits 100% of the sequentially redundant faults can be eliminated in very reasonable amounts of time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Many applications of inverse optimization (IO) arise in settings where the goal is to predict the future actions of an optimizing agent (e.g., an optimizing customer's future purchases). The majority of papers in this area implicitly assume an alternative‐based modeling approach: The forward model finds an optimal set of actions (decisions) from among a given set of alternatives, while the inverse model imputes objective function coefficients corresponding to these alternatives. Since the imputed weights correspond only to alternatives existing in the training set, alternative‐based modeling is limited to applications where the set of options does not change when a prediction is needed. In this paper, we apply an attribute‐based perspective, which allows IO to impute the weights of attributes that lead to an optimal decision instead of imputing the weight of the decision itself. This perspective expands the range of IO applicability; we demonstrate that it facilitates the application of IO in assortment optimization, where changing product selections is a defining feature and accurate predictions of demand are important. We compare inverse attribute‐based optimization with rank‐based and machine learning methods. We show that since IO encodes the utility optimizing behavior of the consumer into the preference learning process, it results in lower assortment regret for the store and a lower utility gap for the consumers.

Coupled experimental-modeling analyses of heat transfer in ex-vivo VS55-perfused porcine hepatic tissue being plunged in liquid nitrogen for vitreous cryopreservation

This paper presents a method for modeling MOS combinational logic gates. Analyses are given for power consumption, output response delay, output response waveshape, and input capacitance. The models are both computationally efficient and accurate, typically lying within 5% of SPICE estimates. They are pertinent to simulation and optimization applications. A general macromodeling software support package is described. A related paper [1] discusses a circuit optimizer based on these models.

Precise modeling of the program heap is fundamental for understanding the behavior of a program, and is thus of significant interest for many optimization applications. One of the fundamental properties of the heap that can be used in a range of optimization techniques is the sharing relationships between the elements in an array or collection. If an analysis can determine that the memory locations pointed to by different entries of an array (or collection) are disjoint, then in many cases loops that traverse the array can be vectorized or transformed into a thread-parallel version. This paper introduces several novel sharing properties over the concrete heap and corresponding abstractions to represent them. In conjunction with an existing shape analysis technique, these abstractions allow us to precisely resolve the sharing relations in a wide range of heap structures (arrays, collections, recursive data structures, composite heap structures) in a computationally efficient manner. The effectiveness of the approach is evaluated on a set of challenge problems from the JOlden and SPECjvm98 suites. Sharing information obtained from the analysis is used to achieve substantial thread-level parallel speedups.

In this manuscript we have described the features of quantum theory that potentially support a more powerful model of computation than that of the classical Turing model. Specifically, we have described how a unitary operator can be applied to quantum superposition of states to transform the entire set of states in parallel. This so-called quantum parallelism is what potentially permits quantum algorithms to achieve computational complexities superior than those of any classical alternatives. Grover’s quantum search algorithm is an example of a fundamental quantum technique that has applications in a wide range of compute-intensive applications ranging from databases to computational geometry to virtual reality. Shor’s quantum factoring algorithm is much more limited in its range of applications but no less important in its theoretical and practical significance.

© 2019 by the authors. Licensee MDPI, Basel, Switzerland. Water-soluble, non-starch polysaccharides fromplants are used commercially in a wide range of food and non-food applications. The increasing range of applications for natural polysaccharides means that there is growing demand for plant-derived polysaccharides with different functionalities. The geographical isolation of New Zealand and its unique flora presents opportunities to discover new polysaccharides with novel properties for a range of applications. This review brings together data published since the year 2000 on the composition and structure of exudate gums, mucilages, and storage polysaccharides extracted from New Zealand endemic land plants. The structures and properties of these polysaccharides are compared with the structures of similar polysaccharides from other plants. The current commercial use of these polysaccharides is reviewed and their potential for further exploitation discussed.

The Leap Motion Controller (LMC) is a low-cost markerless optical sensor that performs measurements of various parameters of the hands that has been investigated for a wide range of different applications. Research attention still needs to focus on the evaluation of its precision and accuracy to fully understand its limitations and widen its range of applications. This paper presents the experimental validation of the LMC device to verify the feasibility of its use in assessing and tailoring wrist rehabilitation therapy for the treatment of physical disabilities through continuous exercises and integration with serious gaming environments. An experimental set up and analysis is proposed using an industrial robot as motion reference. The high repeatability of the selected robot is used for comparisons with the measurements obtained via a leap motion controller while performing the basic movements needed for rehabilitation exercises of the human wrist. Experimental tests are analyzed and discussed to demonstrate the feasibility of using the leap motion controller for wrist rehabilitation.

Energy consumption is a major concern in many embedded computing systems. Several studies have shown that cache memories account for about 50% of the total energy consumed in these systems. The performance of a given cache architecture is largely determined by the behavior of the application using that cache. Desktop systems have to accommodate a very wide range of applications and therefore the manufacturer usually sets the cache architecture as a compromise given current applications, technology and cost. Unlike desktop systems, embedded systems are designed to run a small range of well-defined applications. In this context, a cache architecture that is tuned for that narrow range of applications can have both increased performance as well as lower energy consumption. We introduce a novel cache architecture intended for embedded microprocessor platforms. The cache can be configured by software to be direct-mapped, two-way, or four-way set associative, using a technique we call way concatenation, having very little size or performance overhead. We show that the proposed cache architecture reduces energy caused by dynamic power compared to a way-shutdown cache. Furthermore, we extend the cache architecture to also support a way shutdown method designed to reduce the energy from static power that is increasing in importance in newer CMOS technologies. Our study of 23 programs drawn from Powerstone, MediaBench and Spec2000 show that tuning the cache's configuration saves energy for every program compared to conventional four-way set-associative as well as direct mapped caches, with average savings of 40% compared to a four-way conventional cache.

The development of large scale distributed sensor systems is a significant scientific and engineering challenge, but they show great promise for a wide range of applications. The capability to sense and integrate spatial information with other elements of a sensor application is critical to exploring the full potential of these systems. In this article we discuss the range of application requirements, introduce a taxonomy of localization mechanisms, and briefly discuss the current state of the art in ranging and positioning technologies. We then introduce two case studies that illustrate the range of localization applications.