Geometric-component modeling in charge-pumping technique

In this paper, we have modeled the results of negative bias temperature instability (NBTI) degradation obtained by using charge pumping and linear drain current techniques in the same time measurement setup. The proposed model is based on Hydrogen molecule (H2) cracking at trapped hole center (E' center) to explain the decrease of oxide trapped charge at long NBTI stress time (t > 1000s). In fact, according to experimental data, which are obtained in the framework of the above cited setup, NBTI induces oxide trap generation at earlier stress time followed later by a decrease (annealing) at long stress time. This behavior looks like annealing in radiation effect on gate oxide in MOSFET, which is explained by H2 cracking model. Based on this similarity, we extended this model to NBTI effect. The extended model presents a perfect correlation with the experimental data.

To assess the impact of strain on negative bias temperature instability (NBTI), systematic studies were performed on devices with polycrystalline-Si/SiON as well as deposited metal gate/high-kappa and FUSI/high-kappa gate stacks. The effects of compressive stress, which acts as performance booster for PMOS devices, were studied, with strain introduced by stressor layers as well as SiGe source/drain techniques. Care was taken to account for side effects of processing steps used to introduce the strain, such as changes on threshold voltage or capacitance equivalent thicknesses, in order to obtain a fair evaluation of the intrinsic effect of strain on NBTI. NBTI measurements were complemented by charge pumping and noise measurements to obtain a comprehensive understanding of defects present and of their generation under stress. In addition, nanobeam diffraction strain measurements, as well as curvature mass simulations, were performed in order to investigate the impact of strain on carrier mobility in the vertical direction. Our studies showed consistently that there is no significant degradation of intrinsic NBTI behavior due to process-induced strain.

The life time of RF front end in wireless sensor networks (WSN) is so important that it decides whether the whole system can work normally for a long time. Under CMOS technology, negative bias temperature instability (NBTI) is one of the most important factors that decide chips' life time. Especially with the feature size declining, NBTI effect is becoming more and more serious. Previous works mainly focus on NBTI effect at device level, or NBTI effect in large-scale digital circuits. In this paper, for the WSN node, we study the NBTI impact on the front- end circuits, such as voltage-controlled oscillators (VCO), charge pump (CP), low noise amplifier (LNA), and the whole transceiver system. The circuit level NBTI degeneration models are built for the key modules and the entire transceiver. The mathematical models can be summarized into a conclusion that the phase noise of the VCO will deteriorate, the current mismatch of the CP and the noise figure of the LNA will both increase, and then the sensitivity and adjacent channel selectivity (ACS) will be depressed by NBTI. Under HJTC 0.18-mum technology, our conclusions are proved by the simulation results.

The tremendous scaling of the semiconductor devices is producing the high-density integrated circuits (ICs). Metal-oxide-semiconductor field-effect transistors (MOSFETs) are the basic building blocks for the ICs. The lower area requirement with increased numbers of devices on a substrate makes it an interesting field of very-large-scale integration (VLSI) design. The reliability of the logic circuits is the concern issue in modern-era electronics. Reliability affects the overall performance of the logic circuits and possibility to the failure of the semiconductor devices. Negative bias temperature instability (NBTI) degradation is the major concern in ultra-deep submicron (DSM) regime. The negative threshold voltage of PMOS device when shifted in NBTI effect causes performance degradation over the time. NBTI degradation is the aging effect for PMOS device. This chapter presents the overview of NBTI effect and its possible solution.

A detailed experimental and modeling study of the geometric current component in charge pumping measurements is carried out for bulk MOSFETs. Nand p-channel devices with various gate lengths and widths are studied. Electron and hole components in the charge-pumping current are separated by applying five terminal measurements. A transient two-dimensional numerical model is used for a rigorous analysis of the effect. A one-dimensional semi-analytical model of the free-carrier removal from the channel is developed and applied with proper boundary conditions at the channel ends. The usually applied results from the CCD-theory are found to be inadequate to model the geometric component in MOSFETs. The proposed semi-analytical model enables understanding of all effects observed in experiments and numerical modeling, and provides results which quantitatively agree with numerically calculated curves. The impact of the inversion gate bias, the pulse fail (rise) time and the junction reverse bias on the geometric component is explained. Both experiments and modeling show that the turn-off slew rate is the only parameter of the gate pulse practically relevant for the magnitude of the geometric component.

Trench DMOS interface trap characterization by three-terminal charge pumping measurement

In the charge pumping (CP) measurement of polycrystalline Si (poly-Si) thin-film transistors (TFTs), an experimental approach is developed to evaluate and separate the geometric current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">geo</sub> ) from the measured CP current based on a group of TFTs with different channel widths and fixed channel length. Along with the separation of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">geo</sub> , a new method is proposed to reliably characterize the trap state density of TFTs. Without the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">geo</sub> , the overestimation in CP measurement is avoided even for short CP pulse transition times. Moreover, critical transition time for the occurrence of geometry effect is determined, which agrees well with the prediction from a physical model of diffusion controlled carrier evacuation.

Analyzed herein is the effect of different germanium (Ge) concentrations on negative bias temperature instability (NBTI) and channel hot carrier (CHC) degradations in high-performance Si1-xGex pMOSFETs. It is shown that higher concentrations result in less NBTI degradation due to the increased barrier height between the SiGe and high-k dielectric interface, but it causes greater CHC degradation due to the decreased channel bandgap with higher Ge concentrations. Therefore, the tradeoff between NBTI and HC degradations for different Ge concentrations should be considered when developing high-performance Si1-xGex pMOSFETs.

Power-gating (PG) techniques have been widely used in modern digital ICs to reduce their standby leakage power during idle periods. Meanwhile, virtual supply voltage (VVDD) of a power-gated IC is a function of strength of a PG device and total current flowing through it. Thus, the VVDD level becomes susceptible to 1) negative bias temperature instability (NBTI) degradation that weakens the PG device over time and 2) temporal temperature variation that affects active leakage current (thus total current) of the IC. To account for the NBTI degradation, the PG device must be upsized such that it guarantees a minimum VVDD level that prevents any timing failure over chip lifetime. Moreover, the PG device is also sized for the worst-case voltage drop partly resulted by a large amount of active leakage current at high temperature. However, increasing the size of the PG device to consider both effects leads to higher VVDD (thus active leakage power) than necessary at low temperature and/or in early chip lifetime. To minimize active leakage power increase due to these effects, we propose two techniques that adjust strength of a PG device based on its usage and IC's temperature at runtime. Both techniques are applied to an experimental setup modeling total current consumption of an IC in 32nm technology and their efficacy is demonstrated in the presence of within-die spatial process and temperature variations. On average of 100 die samples, they can reduce active leakage power by up to 10% in early chip lifetime.

Instead, the classical consideration that the geometric component in charge pumping method (CP) is parasitic component, in this work we demonstrate that this component can be used to estimate the negative bias temperature (NBTI) induced mobility degradation using the charge pumping based method such as on- the-fly interface trap (OTFIT).

Negative Bias Temperature Instability (NBTI) is a serious reliability issue for pMOS transistors. Normally, degradation due to NBTI is modeled based on test structure data or ring oscillators embedded within product die. In this paper, we present a new method to determine the NBTI model parameters through I/O circuit measurements. We determine a relationship between Δ V th and signature signal degradation and fit a model to the simulation results. The signature signal involves the calculation of the degradation in the voltage signature, measured as delay and amplitude shifts. Given an estimate of Δ V th we find NBTI model parameters. Then, using the NBTI parameters at test conditions, we scale to use conditions and calculate lifetime. The methodology enables the extraction of NBTI model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to identify chips that are more vulnerable to NBTI.

In this work, we present a novel methodology to independently extract the interface-trap and border-trap generated by negative bias temperature instability (NBTI). It is mainly based on charge pumping technique (CP) at low and high frequencies. We emphasize on the easy-use of this approach and demonstrating its viability to characterize the NBTI. Using alternatively on the fly high and low frequencies CP measurements, it can separate the interface-traps and border-trap (switching oxide-trap) densities as well as their contributions to the threshold voltage shift in the same timeframe, without needing additional methods. The results show a power-law time-dependence of interface- and border-trap with an average exponent n of 0.16 and 0.07, respectively. In addition, it allows device lifetime projection at working conditions.

Negative Bias Temperature Instability (NBTI) is one of the dominant factors determining a device lifetime. NBTI causes a threshold voltage shift on a PMOS transistor. Modern LSI often has large on-chip SRAMs such as cache memories. NBTI affects the SRAM cell as degradation in Static Noise Margin (SNM), which is a measure of the read stability of the cell. Hence, a special technique for mitigating NBTI on on-chip SRAMs is required. We investigate features of NBTI via detailed simulations and find that a stress probability and a stress-recovery cycle are important parameters for mitigating it. These parameters are dependent upon the values stored in the cell and the value is dependent upon the on-chip memory configurations and applications. This paper presents the relationship among NBTI degradation, memory configurations, and target applications by focusing on the values stored in SRAM cells. Furthermore, these observations lead us to discuss guidelines for mitigating NBTI degradation of on-chip SRAMs.

Charge-pumping (CP) technique is proposed to simultaneously measure the border traps and interface-trap density <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(D_ it)$</tex> . The charge pumped per cycle <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(Q_ cp)$</tex> versus high level <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_h)$</tex> of gate pulse for various frequencies was used to observe the behavior of the bulk traps close to the interface as a function of the CP frequency. Evolution on <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$Q_ cp$</tex> as a function of frequency was successfully used to determine the depth profile of border-trap density near the high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$kappa$</tex> gate dielectric/Si interface. The influence of border trap in high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$kappa$</tex> dielectric on the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$D_ it$</tex> measurement can be prevented by an appropriate selection of gate frequency in CP technique.

Negative bias temperature instability (NBTI) degradation of p-channel metal–oxide–semiconductor field effect transistors ( p-MOSFETs) is significantly underestimated by using the conventional characterization techniques due to a severe NBTI recovery during the measurements. In this work, a simple characterization method based on the single-point measurement of the saturated drain current is proposed to minimize the unwanted recovery effect. This method is accurate as is proven by a carefully-designed experiment. With this new proposed method, the measurement time is reduced to tens of milliseconds. This method gives a closer-to-real threshold voltage shift, and yields a more reliable power-law factor and thus a more realistic NBTI picture.