Trench DMOS interface trap characterization by three-terminal charge pumping measurement

A semi-analytical-model is proposed to predict the geometric component in charge pumping (CP) measurements for transistors. It is based on contributing of active CP-area and low-level voltage (V L ) of the gate signal, thermal diffusion, drift field, and self-induced drift field. The calculated I CP -V L characteristics with geometric component model are found in good correlation with the experimental I CP -V L data and are more accurate than the calculated CP without geometric component. This modeling approach can be extended for MOSFET stress reliability evaluation such as negative bias temperature instability (NBTI) and radiation degradations.

In the charge pumping (CP) measurement of polycrystalline Si (poly-Si) thin-film transistors (TFTs), an experimental approach is developed to evaluate and separate the geometric current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">geo</sub> ) from the measured CP current based on a group of TFTs with different channel widths and fixed channel length. Along with the separation of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">geo</sub> , a new method is proposed to reliably characterize the trap state density of TFTs. Without the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">geo</sub> , the overestimation in CP measurement is avoided even for short CP pulse transition times. Moreover, critical transition time for the occurrence of geometry effect is determined, which agrees well with the prediction from a physical model of diffusion controlled carrier evacuation.

Traditional charge pumping (CP) technique relies on trap-assisted recombination from the source/drain to the body contact to characterize interface trap density (Nit) of classical bulk MOSFETs. A variant of the technique called single pulse CP (SPCP) allows interface trap characterization even if the bulk contact is absent, as in silicon-on-insulator (SOI) MOSFET. Unfortunately, neither technique is useful for devices with source-body-tied (SBT) and inhomogeneous channel doping profile, as in lateral diffused MOS (LDMOS) power transistors. Here, we propose a generalization of the CP/SPCP techniques, called Super SPCP (S2PCP), to extract position-resolved localized degradations (ΔNit) in an SBT LDMOS. Careful TCAD modeling and experimental characterizations demonstrate the effectiveness of the proposed approach. Our analysis provides deep insights into the physics of the SPCP technique, demonstrating that the approach can be used to characterize a variety of transistors with nontraditional doping profiles and contact configurations.

Detailed analysis of charge pumping and IdVg hysteresis for profiling traps in SiO 2/HfSiO(N)

Explores the MOS interface-trap charge-pump as an ultralow constant-current generator for analog CMOS applications. Charge pumping techniques in general are more suitable than conventional continuous-time techniques for ultralow current generation because the linear controllability of current by frequency is maintained regardless of the level of current. An interface-trap pump has the same property but the minimum charge it puts out per cycle is at least two orders of magnitude smaller than that of a switched-capacitor charge pump. This helps generate the same current more accurately at a much higher frequency with a much smaller filter capacitance. The paper presents a simplified model of the terminal characteristics of the interface-trap pump and an evaluation of its performance as a stand-alone current generator. Cascoding and complementary pumping are introduced as measures of performance improvement. Temperature sensitivity, pulse feedthrough, controllability, matching, reliability, and trimming issues are addressed. Transconductor circuits built with the charge pump are presented and experimentally evaluated.

Charge-pumping (CP) technique is proposed to simultaneously measure the border traps and interface-trap density <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(D_ it)$</tex> . The charge pumped per cycle <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(Q_ cp)$</tex> versus high level <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_h)$</tex> of gate pulse for various frequencies was used to observe the behavior of the bulk traps close to the interface as a function of the CP frequency. Evolution on <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$Q_ cp$</tex> as a function of frequency was successfully used to determine the depth profile of border-trap density near the high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$kappa$</tex> gate dielectric/Si interface. The influence of border trap in high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$kappa$</tex> dielectric on the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$D_ it$</tex> measurement can be prevented by an appropriate selection of gate frequency in CP technique.

In this work, a set of LDD NMOS transistors are used as test structures for a modified charge pumping technique (LDD charge pumping) to directly measure the interface state density in the LDD region. The technique is validated by measurements on virgin samples and those subjected to hot carrier stress and Fowler-Nordheim stress, which are known to cause different amounts of degradation of the interface over the LDD region and that over the channel region. GIDL current measurements are shown to be in agreement with the charge pumping results. By combining the LDD charge pumping technique with gate to drain capacitance measurements, the lateral profile of the interface state density in the overlap region is obtained.

Charge pumping technique is investigated to identify biomolecular charge polarity using a nanogap-embedded biotransistor. Biomolecules immobilized in a nanogap provide additional charges in the gate dielectric. They give rise to a change in the charge pumping current, as detected by applying a designed pulse waveform. The measured results are analyzed with the aid of numerical simulations. The proposed charge pumping technique represents an insightful method of investigating the electrical properties of biomolecules beyond biosensing.

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO 2/HfO 2 gate stack nMOSFETs

In this work, a charge pumping characterization has been carried out on 4H-SiC nMOSFETs built with different SiC doping processes. Because charge pumping (CP) measurements on SiC are complex to implement, three different CP methods have been used for Dit characterization. The impact of geometrical and electrical parameters on each method is studied. Finally, it is detailed the full measurement flow chosen for a deeper and more accurate understanding of Dit electrical characterization.

The emerging Phase Change Memory (PCM) technology exhibits excellent scalability and density potentials. At the same time, they require high current and high voltages to switch cell states. Their working voltages are provided by CMOS-compatible on-chip charge pumps (CPs). Unfortunately, CPs and particularly those for RESET, have a large parasitic power (a dominant component in total power loss) during operations, which significantly degrades their energy efficiency. In addition, CPs seriously suffer from the Time-Dependent Dielectric Breakdown (TDDB) problem due to their boosted operation voltage. To maintain a reasonable lifetime of CPs, existing solutions actively switch them on per-operation basis, resulting in large performance degradation. In this paper, we address the above issues through two designs - Reset_Sch (RESET scheduling) and CP_Sch (CP scheduling). Reset_Sch schedules when to perform a RESET for different cells upon writing a PCM line. It significantly reduces the power loss, and peak working power of RESET CP. CP_Sch incorporates a fast READ CP design to provide fast charge-up time for reads and minimize performance penalty. Our experimental results show that on average, 70%of power loss for RESET CP can be reduced; and performance loss can be reduced from 16% to 2% while achieving a 16% improvement in reliability.

In this paper, we study the interface traps during program/erase (P/E) cycles. By using charge pumping measurement, the charge pumping currents (ICP) of the serial P/E cycled states are compared to the initial one. The ICP decreases after the programmed operation under a constant temperature within 5 P/E cycles. The observation on the recovery of the interface states has been attributed to the hot electron injection stress.

In this study, the gamma ray radiation effect on the characteristics of inkjet-printed semiconducting single-walled carbon nanotubes (sSWCNTs) thin-film transistors (TFTs) is investigated. The devices with top gate dielectrics consisted of BaTiO3 and poly(methyl methacrylate) (PMMA) were characterized before and after 150 krad 60Co gamma radiation in air. It reveals that the radiation results in a positive threshold voltage shift from -0.5 to 3.6 V (with a drain voltage biased at -1 V). The hysteresis decreases slightly from 1.2 to 0.5 V, indicating that the BaTiO3/PMMA dielectric layer effectively encapsulates the sSWCNTs TFTs from absorbing molecules in the environment. Furthermore, the charge pumping current ICP is measured with a gate voltage pulsed at 100 kHz. The maximum ICP increases from 90 to 140nA, which translates to an increase in the interface trap density from 4.5×1011 to 1.1×1012 cm-2eV-1. The charge pumping measurements at the frequency of 10∼250 kHz show that the increase of ICP induced by radiation is obvious when f&amp;gt;30 kHz but is little when f&amp;lt;30 kHz, which indicates that the radiation induced charge traps locate near sSWCNTs. The BaTiO3/PMMA gate dielectric remains to be a good insulator with a leakage current of less than 60 pA after radiation. Such printed flexible TFTs with the polymer gate dielectric possess similar radiation tolerant compared to convention devices on rigid substrates.

In this paper, we have modeled the results of negative bias temperature instability (NBTI) degradation obtained by using charge pumping and linear drain current techniques in the same time measurement setup. The proposed model is based on Hydrogen molecule (H2) cracking at trapped hole center (E' center) to explain the decrease of oxide trapped charge at long NBTI stress time (t > 1000s). In fact, according to experimental data, which are obtained in the framework of the above cited setup, NBTI induces oxide trap generation at earlier stress time followed later by a decrease (annealing) at long stress time. This behavior looks like annealing in radiation effect on gate oxide in MOSFET, which is explained by H2 cracking model. Based on this similarity, we extended this model to NBTI effect. The extended model presents a perfect correlation with the experimental data.

The interfacial density of states (Dit) distribution of high-κ dielectric Ga2O3(Gd2O3) [GGO] directly deposited on n-type Ge(100) without invoking any interfacial passivation layer (IPL) was established using conductance measurements and charge pumping (CP) technique. The conductance measurements yielded Dit values in the range of (1–4)×1011 cm-2 eV-1 from the mid-gap energy to the conduction band edge within the Ge band gap, which are consistent with the mean Dit value of ∼2×1011 cm-2 eV-1 near the mid-gap obtained independently by the CP method. The flat Dit distribution at the conduction band edge compares favorably with those attained using IPLs such as SiO2/Si-cap and GeO2.