Super Single Pulse Charge Pumping Technique for Profiling Interfacial Defects

In this article, the three-phase ON-state resistance (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>on</roman></sub>) degradation mechanisms are thoroughly investigated in a shallow trench isolation (STI)-based laterally diffused MOS (LDMOS). The charge-pump (CP) experiments and extensive simulations reveal that the initial <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>on</roman></sub> degradation is primarily dominated by hot-carrier injection (HCI) effects at the source-side bottom corner of STI. To solve it, a novel hot-carrier suppression (HCS) technique is proposed to modulate the electric fields and thereby suppress the HCI effects at this critical location. After optimization, the fabricated HCS LDMOS exhibits a significantly improved HCI immunity, with maximum <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>on</roman></sub> degradation limited to less than 0.75%, 0.62%, and 0.80% at <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>gs</roman></sub> = 1, 3, and 5 V, respectively, reduced around 3.39%, 1.59%, and 2.45% when compared to the conventional LDMOS.

Trench DMOS interface trap characterization by three-terminal charge pumping measurement

Nature and location of interface traps in RF LDMOS due to hot carriers

Charge-pumping (CP) technique is proposed to simultaneously measure the border traps and interface-trap density <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(D_ it)$</tex> . The charge pumped per cycle <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(Q_ cp)$</tex> versus high level <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_h)$</tex> of gate pulse for various frequencies was used to observe the behavior of the bulk traps close to the interface as a function of the CP frequency. Evolution on <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$Q_ cp$</tex> as a function of frequency was successfully used to determine the depth profile of border-trap density near the high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$kappa$</tex> gate dielectric/Si interface. The influence of border trap in high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$kappa$</tex> dielectric on the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$D_ it$</tex> measurement can be prevented by an appropriate selection of gate frequency in CP technique.

Introduction While wireless communications standards may come and go with developments in the latest digital coding technology, or the liberation of new fragments of the electromagnetic spectrum, the common denominator among the various communications systems is the power amplifier. Over the last few decades, the transition from vacuum tubes and other forms of amplification to solid state devices has been almost complete, especially at power levels less than 1 kW. Nowadays, at the heart of the power amplifier, we find the power transistor. In the world of RF wireless communications, the base-stations and long range transmitters use silicon LDMOS (laterally-diffused MOS) high power transistors almost exclusively. In addition to modern cellular communication systems, LDMOS devices are also used in a wide range of applications requiring radio-frequency power amplification: HF, VHF, and UHF communications systems; pulsed radar; industrial, scientific and medical (ISM) applications; avionics; and most recently in WiMAX™ communication systems. The frequency range of these applications is from a few megahertz and up to 4 GHz. While LDMOS technology is pre-eminent in high-power RF and lower frequency microwave applications, a wide variety of compound (III–V) semiconductors are used as effective power amplification devices, especially for application frequencies above about 5 GHz, and also for lower power applications such as cellular handsets, Bluetooth™ and other wireless local area networks (WLANs), which generally demand output powers of about 1 watt or below.

Explores the MOS interface-trap charge-pump as an ultralow constant-current generator for analog CMOS applications. Charge pumping techniques in general are more suitable than conventional continuous-time techniques for ultralow current generation because the linear controllability of current by frequency is maintained regardless of the level of current. An interface-trap pump has the same property but the minimum charge it puts out per cycle is at least two orders of magnitude smaller than that of a switched-capacitor charge pump. This helps generate the same current more accurately at a much higher frequency with a much smaller filter capacitance. The paper presents a simplified model of the terminal characteristics of the interface-trap pump and an evaluation of its performance as a stand-alone current generator. Cascoding and complementary pumping are introduced as measures of performance improvement. Temperature sensitivity, pulse feedthrough, controllability, matching, reliability, and trimming issues are addressed. Transconductor circuits built with the charge pump are presented and experimentally evaluated.

A semi-analytical-model is proposed to predict the geometric component in charge pumping (CP) measurements for transistors. It is based on contributing of active CP-area and low-level voltage (V L ) of the gate signal, thermal diffusion, drift field, and self-induced drift field. The calculated I CP -V L characteristics with geometric component model are found in good correlation with the experimental I CP -V L data and are more accurate than the calculated CP without geometric component. This modeling approach can be extended for MOSFET stress reliability evaluation such as negative bias temperature instability (NBTI) and radiation degradations.

Charge pumping technique is investigated to identify biomolecular charge polarity using a nanogap-embedded biotransistor. Biomolecules immobilized in a nanogap provide additional charges in the gate dielectric. They give rise to a change in the charge pumping current, as detected by applying a designed pulse waveform. The measured results are analyzed with the aid of numerical simulations. The proposed charge pumping technique represents an insightful method of investigating the electrical properties of biomolecules beyond biosensing.

In this work, a set of LDD NMOS transistors are used as test structures for a modified charge pumping technique (LDD charge pumping) to directly measure the interface state density in the LDD region. The technique is validated by measurements on virgin samples and those subjected to hot carrier stress and Fowler-Nordheim stress, which are known to cause different amounts of degradation of the interface over the LDD region and that over the channel region. GIDL current measurements are shown to be in agreement with the charge pumping results. By combining the LDD charge pumping technique with gate to drain capacitance measurements, the lateral profile of the interface state density in the overlap region is obtained.

LDMOS is one of the most widely used power transistors and has a variety of applications across multiple sectors (automobile, photovoltaics, communication, etc.). Unfortunately, the high applied bias makes Hot Carrier Degradation (HCD) a persistent reliability concern for LDMOS transistors. HCD occurs due to the generation of interface defects (N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</inf> ) by energetic electrons/holes, and the degradation rate depends sensitively on gate/drain voltages, doping, and transistor geometry. Several efforts have been made to model HCD in TCAD to predict the HCD susceptibility of next-generation LDMOS transistors. However, the lack of characterization techniques to extract N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</inf> (x) in LDMOS makes it difficult to cross-check ΔN <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</inf> (x) obtained from the TCAD models, thereby making reliability aware predictive design difficult. In this paper, we: (a) determine the physical mechanism of HCD in a planar LDMOS using TCAD; (b) demonstrate the capability of the Super Single Pulse Charge Pumping (S <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> PCP) technique to extract N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</inf> (x) at various points in the LDMOS, (c) quantify the spatial and temporal evolution of N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</inf> (x,t), and compare the experimental results with TCAD predictions; (d) identify the key differences between the experimental and TCAD approach and suggest possible physical mechanisms responsible. This analysis establishes the robustness and identifies the limitations of TCAD modeling of HCD in LDMOS devices.

In this paper, we have modeled the results of negative bias temperature instability (NBTI) degradation obtained by using charge pumping and linear drain current techniques in the same time measurement setup. The proposed model is based on Hydrogen molecule (H2) cracking at trapped hole center (E' center) to explain the decrease of oxide trapped charge at long NBTI stress time (t > 1000s). In fact, according to experimental data, which are obtained in the framework of the above cited setup, NBTI induces oxide trap generation at earlier stress time followed later by a decrease (annealing) at long stress time. This behavior looks like annealing in radiation effect on gate oxide in MOSFET, which is explained by H2 cracking model. Based on this similarity, we extended this model to NBTI effect. The extended model presents a perfect correlation with the experimental data.

The interfacial density of states (Dit) distribution of high-κ dielectric Ga2O3(Gd2O3) [GGO] directly deposited on n-type Ge(100) without invoking any interfacial passivation layer (IPL) was established using conductance measurements and charge pumping (CP) technique. The conductance measurements yielded Dit values in the range of (1–4)×1011 cm-2 eV-1 from the mid-gap energy to the conduction band edge within the Ge band gap, which are consistent with the mean Dit value of ∼2×1011 cm-2 eV-1 near the mid-gap obtained independently by the CP method. The flat Dit distribution at the conduction band edge compares favorably with those attained using IPLs such as SiO2/Si-cap and GeO2.

In this work, we present for the very first time, at our knowledge, results obtained by performing the two level charge pumping (CP) technique on nano-crystal memory devices. The charge pumping method allows the determination of the silicon dots characteristics such as their density, their spatial distribution within the dielectric and their effective diameter.

A novel charge pumping technique is proposed for measuring the spatial distribution of interface state density N/sub it/ in MOSFETs. Instead of connecting the source and the drain together as is usually done, different reverse bias voltages are applied to the source and the drain separately. The method makes it possible to measure the distribution of N/sub it/ without making any assumptions about it. With this method, one can determine N/sub it/ distribution near the source and the drain of the channel independently. Results show that the interface state distribution of a virgin MOSFET is not constant along the channel. >

In this paper, we have used the partially depleted SOI MOSFET to measure the intensity of light. The charge pumping technique was used to get rid of the photogenerated carriers in the body in an attempt to keep the drain current constant. Using this technique flux densities as low as 2 mW/m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> were measured.