Grayscale control algorithm based on optokinetic nystagmus

The use of the VHSIC Hardware Description Language (VHDL) has become very important to the simulation and implementation of digital systems in both industry and educational settings. Although VHDL is a powerful language with many capabilities, it has downfalls when considering the difficulty in learning the language as well as its limited capabilities for transitioning a design from initial concept to design entry and verification stages. This paper discusses techniques used to teach the VHDL design methodology to graduate students, as well as methods used to go through a complete design cycle from initial concept to final implementation. VHDL design techniques were developed using various projects and homework assignments, and different approaches to implementing the same function allowed direct comparisons of the speed and size of the designs. Different processes for taking a design from initial concept through chip implementation were discussed, and one example of the process is discussed here. A Finite Impulse Response (FIR) filter was conceptually designed using the MATLAB programming environment to determine adequate performance specifications such as filter size and quantization levels. The design was then written using a behavioral VHDL coding style, as well as a VHDL test bench to determine if the VHDL behavioral model provided the same results as the MATLAB model. After design synthesis of the behavioral description using Synopys tools, the same test bench was used again to verify the performance of the structural VHDL netlist with annotated place and route delay information provided from the Alters MaxPluslI tools. Final verification took place with at the board level using an Altera CPLD programmed with the FIR filter design.

Flat-panel displays (FPDs) will soon become ubiquitous products in our homes, workplaces, and a number of places in between. Familiar display applications pioneered by the venerable cathode-ray tube (CRT) will progressively utilize a number of different FPDs. Flat-panel displays will also initiate and pioneer new applications, as was the case with notebook computers and personal digital assistants.The future proliferation of FPDs can no longer be doubted for two simple reasons. First, such devices help us cope with this already information-saturated society. Second, the technological momentum and financial commitment needed for FPDs to take hold are already irreversibly set in place. It is the insatiable current and near-future demand that are pulling the field, and that are fueling a flurry of research and development activities. The display market has grown in size from tens of millions of dollars only a decade ago to a nearly ten-billion-dollar industry. This market growth is expected to continue at a brisk pace during the next decade.This of course is in no way bad news for materials scientists and engineers. We nearly always benefit from development of new and complex products. It is in regard to these rather incipient but advanced manufacturing technologies where we often encounter challenging, relevant, and interesting materials problems. The better we address these obstacles during these early and therefore critical times, the more successful the FPD technology will be in fulfilling the potential opportunities that lie ahead.

Today, in a multimedia age, electronic displays are the essential key devices involved in the relation between multimedia equipment and human beings. Flat panel displays are overcoming the restrictions of traditional CRTs (Cathode Ray Tubes) regarding portability and large screen capability, and they are ready to expand their multimedia application fields. TFT-LCDs (Thin Film Transistor-Liquid Crystal Displays) in particular have advantages such as light weight, low profile, low power consumption, and motion picture display, and importantly contribute the development of multimedia. The color PDP (Plasma Display Panel) features emissive display, a large screen, and a low profile, and mass production aimed at implementing space-saving, and wall-hung HDTV (High Definition Television) is about to be started. Since further development of multimedia is expected in the twenty-first century, the scale of this market is immeasurable. At the same time, the flat panel display market will also expand. Wide variety of flat panel displays will gain wider use as they secure their respective markets through their particular advantages.KeywordsMultimediaDevice technologyElectronic displayFlat panel displayLCDTFT-LCDColor PDP

Modern digital system designs have been predominantly software driven, using the hardware description languages. While there are many different types of the hardware description languages, the most commonly used are VHDL (very high-speed integrated circuit hardware description language) and the Verilog. Both lend themselves to the successful realizations of the digital systems. However, even the experienced designers are often confused about which one to use and their relative performance characteristics. The authors discuss the general features of both languages from a design standpoint. Also, VHDL and Verilog based coding are discussed and the design realizations and simulations of the results are presented. We present the case studies of fundamental digital units such as full adders, comparators, counters and shift registers and discuss the timing and other important aspects which can be integrated into the actual designs. Also, the authors present a working model for hardware realizations using the CPLD (complex programmable logic device) platforms of the software designs. While it is acceptable to functionally check the designs with simulations, in actual applications, there is a need for hardware realizations as well. There are instances where the program code is sequential and the simulation results are also sequential. However, with the present complexity of CPLDs, and FPGAs where some hardware elements can be synthesized in concurrence, there can be timing problems. The authors also examine such instances and provide an insight into the arbitration schemes for a reliable digital system realization.

Chapter 1 - Introduction and Background

This paper describes a direct measuring technique for determining the image auality of raster-scanned cathode-ray tube (CRT) displays. This technique is based on the Modulation Transfer Function (MTF) theory and human visual psychophysical data. The rationale for the technique is discussed from a theoretical as well as functional viewpoint. The instrumentation necessary to obtain these measures in manual and automatic modes is discussed. Data obtained using this measurement technique are analyzed and compared with the theoretical performance of the displays. The image quality of new CRT displays procured for the U.S. Army's Advanced Attack Helicopter is being specified and tested using this direct measuring technique.

The design of increasingly more complex custom and semicustom integrated circuits has traditionally forced the introduction of new design methodologies. Formal specifications, top-down design, and design-for-test have become standard practices for IC design teams. The adoption of VHDL (VHSIC Hardware Description Language), as an IEEE standard (IEEE-1076), and the recent availability of design automation tools supporting VHDL, has begun yet another wave of change in the ASIC design process. The author investigates the impact of VHDL on the ASIC design team, as well as on the ASIC manufacturer. It is his intention to identify areas which must be investigated by the ASIC community before incorporating VHDL in the design process. >

The VHDL Design Exchange Group (VDEG), which consists of VHDL (VHSIC hardware description language) suppliers and users, was formed to promote the identical operation of VHDL models on different tools. One task of VDEG, which is still ongoing, is to develop a consensus logic model and a method for its use. VDEG and the VDEG's work on this task as of September 1989 are described. The definition of portability used by VDEG and the minimalist approach toward a standard multivalue logic type for modeling favored by the group are examined. The use of the model is discussed. VDEG is developing a library of packages to aid in the construction of portable models; the package containing definitions of types of operations is described in some detail. Two mappings are presented to illustrate the assertion that the portable logic model is easy to map to the logic models in existing tools. Future work is outlined. >

Induction motors are currently used in many industrial applications. Thus, their control techniques have received a lot of interest. An efficient method of induction motor control is the Direct Torque Control (DTC). It is considered particularly interesting since it is independent of machine rotor parameters and requires no speed or position sensors. This paper presents a simulation of a DTC strategy for three-phase induction motors based on the Field Programmable Gate Array (FPGA) technology. The real controller is not experimentally tested. A specific methodology for the hardware description language in VHSIC Hardware Description Language (VHDL) is presented. This paper summarizes the prior work before implementing the experimental FPGA control of an induction motor. This methodology allows one to verify the behavior of the VHDL codes before their implementation, reducing the risks of significant changes when implemented. The VHDL design technique for DTC-based speed control is designed through the descriptions of coordinate transformation, speed controller, stator flux and torque estimator, stator flux and torque controller, and stator flux position detector. The simulation is performed using the MATLAB/Simulink, DSP Builder, and Quartus II software, on an Altera DE2-115 board. Simulation results verify the validity of the proposed method.   Key words: Digital control, induction motor, digital signal processing, VHSIC Hardware Description Language (VHDL).

Hardware design under the use of the VHSIC hardware description language (VHDL) has to consider three independent property scales that influence the design process from an abstract level to gate level, namely, the design view, the timing aspect, and the value representation. The well-known Y-chart model is not suitable to describe these property scales in a satisfactory way. A new model for the design flow representation with the particular view on VHDL is presented. It is a three-dimensional cube with three coordinates divisions per dimension. Each state of the cube represents a modeling style in VHDL. For the use of more powerful hardware description languages, the cube may be extended to four coordinates per dimension. >

Flat panel displays (FPDs) have simulated a tremendous amount of research interest in the past two decades as replacements for cathode ray tube (CRT) displays in applications where weight, volume, and power consumption are important.

: Purpose: Investigator was to test an invention in electron optics that might allow development of a very high-resolution cathode ray tube (CRT) suitable for digital mammography workstations. Scope: The invention solves a very old problem in electron optics and is patented. The invention allows deflection of a wide beam into large angles using electric fields with little or no acquired aberrations. Major findings: This project was successfully completed. The invention worked as predicted and results have been published in Journal Vacuum Science and Technology - B 20(6): 2678-81, Nov/Dec 2002. Results and Significance: While it is now technically possible to develop such a CRT display device a new flat panel display was announced by IBM that seems to fulfil the mammography application needs. Thus while this project was a technical success, this particular application has been fulfilled by another company's product. We are now looking for other applications where our technology can make a contribution. Fortunately, there are many opportunities ranging from electron beam lithography to isotope separation and mass spectrometry.

To assess and quantify the image quality at two dose levels for an amorphous Silicon (a:Si) Cesium Iodide (CsI) flat panel system compared with a direct amorphous Selenium (a:Se) digital radiography system. A contrast detectability test was performed employing the CDRAD-phantom at mAs-values leading to approximately equal phantom entrance doses of 41.4, 57.9, 75.1 and 120.8 micro Gy for the a:Se and 39.9, 58.4, 75.6 and 117.9 micro Gy for the CsI system. Images were presented to 4 independent observers. For quantitative comparison, the image quality figure (IQF) was calculated. Statistical analysis was performed using Pearson's correlation and the Wilcoxon test. A ROC-analysis was performed employing the TRG-phantom in a high- and a low-dose setting leading to entrance doses of 126.2 and 35 micro Gy for the direct, and 125.9 and 34.4 micro Gy for the indirect system. Statistical significance was evaluated using the Wilcoxon test. The flat panel a:Si digital system provided superior results compared with the a:Se drum digital system with respect to low-dose settings for CDRAD-phantom and ROC-analysis, ensuring a better image quality with respect to contrast and detail detectability. Higher-dose settings provided similar results for both systems. Image quality of a:Si flat panel digital radiography proved to be superior to a:Se drum digital radiography using low-dose settings. If the primary target is dose reduction indirect flat panel technology should be used.

This paper introduces an efficient parallel hardware architecture to implement the Adaptive Vector Median Filter (AVMF) in Field Programmable Gate Array (FPGA). This architecture is developed using the VHSIC Hardware Description language (VHDL) language and integrated in the Hardware/Software (HW/SW) environment as coprocessor. The NIOS II softcore processor is used to execute the SW part. The communication between HW and SW parts is carried out through the Avalon bus. The experimental results on the Stratix II development board show that the HW/SW AVMF system allows a reduction in processing time by 572 times relative to the SW solution at 140MHz with small decrease in image quality.

The electronic display industry is changing in three important ways. First, the dominance of the cathode ray tube (CRT) is being challenged by the development of flat panel displays (FPDs). This will lead to the availability of displays of higher performance, albeit at greater cost. Secondly, the analog interfaces between displays that show data and the computers that generate the data are being replaced by digital connections. Finally, a high-resolution display is becoming the most expensive component in computer system for homes and small offices. It is therefore desirable that the useful lifetime of the display extend over several years and that the electronics allows the display to be used with many different image sources. Hopefully, the necessity of having three or four large CRTs in one office to accommodate different computer operating systems or communication protocols will soon disappear. Instead, we hope to see a set of flat panels that can be switched to show several independent images from multiple sources or a composite image from a single source. The more rapid rate of technological improvements and the higher cost of flat panel displays raise the incentive for greater planning and guidance in the acquisition and integration of high performance displays into large organizations, such as LLNL. The goal of the Digital Display Integration Project (DDIP) is to provide such support. This will be achieved through collaboration with leading suppliers of displays, communications equipment and image-processing products, and by greater exchange of information within the Laboratory. The project will start in October 1999. During the first two years (FY2000-1), the primary focus of the program will be upon: introducing displays with high information content (over 5M pixels); facilitating the transition from analog to digital interfaces; enabling data transfer from key computer platforms; incorporating optical communications to remove length restrictions on data transfer; and optimizing techniques to reduce communications bandwidth. Additional topics that will be addressed include: obtaining greater color control; minimization of seam widths in tiled displays; and the human factors that impact the efficient use of high resolution displays. The scope of the project will include both direct-view displays, for use by individuals and small groups, and projection systems for conference rooms and auditoriums.