Heavy ion-induced single event upset sensitivity evaluation of 3D integrated static random access memory

We measured energy-dependent proton-induced Single Event Upset (SEU) cross sections for sub-100-nm bulk planar Static Random Access Memory (SRAM)-based Field Programmable Gate Arrays (FPGAs) at 10 – 220 MeV. The proton-induced SEU cross sections were compared with neutron-induced SEU cross sections which had been directly measured. Proton- and neutron-induced SEU cross sections were found to be equivalent above 20 MeV, which indicates they are mutually substitutable for the purposes of SEU rate evaluation of sub-100-nm bulk planar SRAM devices.

In this paper, single-event upset (SEU) is predicted using a combination of technology computer aided design (TCAD) and Geant4 Monte Carlo simulations. According to the layout topology of a 65 nm complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) arrays, the sensitive volumes (SVs) of off and on-transistors were calibrated by TCAD using novel circuit schematics. The effects of on-transistor charge collection on SEU were studied, and a novel criterion for SEU occurrence is proposed. Heavy ion simulation results indicate that the probability of SEU recovery increased with increased ion energy and striking tilt. The simulated SEU cross section and multiple cell upsets (MCUs) percentage based on the proposed method are in agreement with the experimental data for 6 T SRAM cells, which were fabricated using 65 nm processing technology.

Single-event performance of 65 nm CMOS SRAM technology was revealed by Monte-Carlo methods, with heavy ions energy ranging from 20 MeV/n to 2 GeV/n. By comparing the energy-deposition spectrums in sensitive volumes (SV) and single event upset (SEU) cross sections, it was found that secondary electrons and nuclear reactions of the 200 MeV/n incident ions have significant impact on the device response. Secondary electrons excited by the energetic space ions can spread beyond the SV of the 65 nm bulk CMOS SRAM and result into partial collection of the ion track. This mechanism causes the constant increase of SEU cross section with ion LET, even deviating from the surface area of the SV by 3.3×. Nuclear reaction can lead to unexpectedly large energy-deposition events in the SV by 10x than the initial LET, which create SEU cross sections in the sub-LET th region, although with lower probability than direct-ionization process by 104×∼105×. Higher ion energy seems to enhance the influence of secondary electrons and nuclear reaction. Moreover, soft error rates of the 65 nm bulk CMOS SRAM technology on GEO were predicted and discussed.

We have performed an irradiation test of low-energy positive and negative muons on 65-nm ultra-thin body and thin buried oxide silicon-on-insulator static random access memories. The single event upset (SEU) cross sections were measured systematically as a function of incident muon momentum and operating supply voltage. The experimental results show that the negative muon SEUs occur at about three times higher rate than the positive muon ones at the supply voltage of 0.5 V when the incident muons stop near the sensitive volume (SV). A Monte-Carlo simulation with the particle and heavy ion transport code system (PHITS) was carried out using a simple SV model. The simulation based on the PHITS using the SV model is found to reproduce generally well the momentum dependence of the measured SEU cross sections for both positive and negative muons. From the simulation, the charged particles and secondary ions having significant influence on SEUs are specified and the differences between negative and positive muons are discussed.

Strong fields of bremsstrahlung photons and photoneutrons are produced during the operation of high-energy electron linacs. Therefore, a mixed gamma and neutron radiation field dominates the accelerators environment. The gamma radiation induced Total Ionizing Dose (TID) effect manifests the long-term deterioration of the electronic devices operating in accelerator environment. On the other hand, the neutron radiation is responsible for Single Event Effects (SEE) and may cause a temporal loss of functionality of electronic systems. This phenomenon is known as Single Event Upset (SEU). The neutron dose (KERMA) was used to scale the neutron induced SEU in the SRAM chips. Hence, in order to estimate the neutron KERMA conversion factor for Silicon (Si), dedicated calibration experiments using an Americium-Beryllium ( 241 Am/Be) neutron standard source was carried out. Single Event Upset (SEU) influences the short-term operation of SRAM compared to the gamma induced TID effect. We are at present investigating the feasibility of a SRAM based real-time beam-loss monitor for high-energy accelerators utilizing the SEU caused by fast neutrons. This paper highlights the effects of gamma and neutron radiations on Static Random Access Memory (SRAM), placed at selected locations near the Superconducting Linear Accelerator driving the Vacuum UV Free Electron Laser (VUVFEL) of DESY.

As the feature size of the device decreases, the critical charge decreases gradually and the influence of radiation particles becomes more and more serious, especially the single event upset (SEU). Some previously unknown radiation damage began to appear as the size of the device decreased. Low energy protons undergoing direct ionization can induce SEU in 65 nm static random access memories (SRAM), and muons can induce errors as a function of incident muon energy. In this work, the radiation damage caused by X-ray to the 45 nm SRAM is studied through experiments. The sensitive volume of SRAM is constructed using Monte Carlo radiation transport code Geant4 to analyze the effects of critical charge and metal interconnect overlayers of different materials. The experimental results suggested that under the low power state, the secondary electrons produced by the X-ray can induce upsets, lower the voltage, and increase the number of errors. Monte Carlo simulation shows that as the critical charge decreased, SEU becomes more severe. At the same time, photons interact with high atomic number materials in the metal interconnect overlayers, which could generate more secondary electrons resulting in the SEU cross section rising to a higher value.

Experimental evidences are presented showing obvious differences in threshold ion range for silicon-on-insulator (SOI) and bulk static random access memories (SRAMs). Single event upset (SEU) cross sections of SOI SRAMs start to decline off the Weibull curve at ion ranges of 20.7 μm to 40.6 μm, depending on the ion species and also the thickness of metallization layers. Whereas for the bulk SRAMs, threshold range of Bismuth beam is unexpectedly larger than 60.4 μm. Underlying mechanisms are further revealed by Monte Carlo simulations and in-depth analysis. The relative location of ion's Bragg peak to the sensitive region and also the position of ion LET in the σ-LET curve of test device turn out to be two key parameters in determining the threshold ion range which can explain the experimental results. Significant discrepancies are observed in the deposited energy spectrums in sensitive regions of bulk SRAM by ions at different sides of the Bragg peak, but with almost the same LET at die surface (all with ion range larger than 30 μm). Energy straggling of incident ions at the die surface is considered by Monte Carlo calculations. Implications for hardness assurance testing are also discussed. A formula is proposed for calculating the “worst case” threshold ion range.

为了提高纠错编码（ECC）的有效性，先进的静态随机存储器（SRAM）多采用位交错结构。但是，在没有物理版图信息的情况下，位交错设计使得从辐照测试数据中提取出多单元翻转（MCU）变得更加困难。运用Bi离子辐照带有ECC的65 nm SRAM器件，研究了该款器件在重离子辐照下的敏感性。为伪多位翻转（FMBU）以及MCU的数据分析提供了理论指导和帮助，完善了判别MCU的基本法则。除此之外，研究结果表明，ECC的汉明编码对于纳米器件的效果不够理想。在未来的空间应用中，需考虑更高层次的编码算法来抵抗单粒子翻转。 In order to improve the robustness of error-correcting codes (ECC), modern static random access memory (SRAM) always use bit-interleaving structure. However, in the absence of physical layout information, the bit-interleaving design makes it more difficult to extract the multiple-cell upset (MCU) from the test data. In this paper, the sensitivity of Bi ion irradiation was investigated in a 65 nm technology SRAM with ECC. The experimental results provide a theoretical guidance and help for the fake multiple-bit upset (FMBU) and MCU data analyzing, which improve and perfect the basic rules extracting MCU from the test data. In addition, the results show that the performance of hamming encoding is not ideal in Nano scale SRAM. In the future of space applications, it is necessary to consider more advanced algorithms to against SEU.

A neutron irradiation test of static random access memories (SRAMs) was performed using a spallation neutron source at Materials and Life Science Experimental Facility (MLF) in the Japan Proton Accelerator Research Complex (J-PARC). The probability of neutron-induced single-event upsets (SEUs) was measured for 65-nm bulk and silicon on thin buried oxide (SOTB) SRAMs under neutron irradiation at the BL10 experimental facility. The measured SEU data were compared with the previous data of the same SRAMs which were measured at other irradiation facilities having different neutron spectra. The differences in the operating voltage dependence of the measured SEU probabilities are discussed with particular attention to the impact of irradiation side on SEUs. The particle and heavy ion transport code system (PHITS) simulation based on the simple sensitive volume model qualitatively reproduced the operating voltage dependence seen in the measured ratio of SEUs for the Bulk SRAM between the resin side and board side irradiations under different neutron fields.

The exposure of spaceborne devices to high-energy charged particles in space results in the occurrence of both a total ionizing dose (TID) and the single-event effect (SEE). These phenomena present significant challenges for the reliable operation of spacecraft and satellites. The rapid advancement of semiconductor fabrication processes and the continuous reduction in device feature size have led to an increase in the significance of the synergistic effects of TID and SEE in static random access memory (SRAM). In order to elucidate the involved physical mechanisms, the synergistic effects of TID and single-event upset (SEU) in a new kind of 130 nm 7T silicon-on-insulator (SOI) SRAM were investigated by means of cobalt-60 gamma-ray and heavy ion irradiation experiments. The findings demonstrate that 7T SOI SRAM is capable of maintaining normal reading and writing functionality when subjected to TID irradiation at a total dose of up to 750 krad(Si). In general, the TID was observed to reduce the SEU cross-section of the 7T SOI SRAM. However, the extent of this reduction was influenced by the heavy ion LET value and the specific writing data pattern employed. Based on the available evidence, it can be proposed that TID preirradiation represents a promising avenue for enhancing the resilience of 7T SOI SRAMs to SEU.

We have performed real-time soft error rate (SER) measurements on bulk 65 nm static random-access memories (SRAMs) during deuterium–deuterium (D-D) plasma operation at W–tungsten– Environment in Steady-state Tokamak (WEST). The present measurement campaign was characterized by the production of several tens of long pulse discharges (~60 s) and by a total neutron fluence (at the level of the circuits under test) up to ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> n.cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , improving the error statistics by a factor of more than 6 with respect to the first measurements obtained in 2020. Experimental results demonstrate the occurrence of bursts of single-event upsets (SEUs) during the most efficient shots and 12% of multiple cell upset (MCU) events. Time-resolved data also show that MCUs are preferentially detected in the last part of these long pulses, providing further evidence that higher energy neutrons, initiated by deuterium–tritium (D-T) reactions due to triton burn-up in the D-D plasma, may play a role in the production of multiple cell upsets that cannot be attributed in such large proportions to “low energy” neutrons produced in D-D reactions.

The impacts of the gate length and width of the transistors on the single event upset (SEU) hardness of static random access memory (SRAM) cells has been investigated by SPICE simulations, biased on a partially depleted (PD) silicon-on-insulator (SOI) CMOS technology. The results show that increasing the gate width can dramatically enhance the linear energy transfer (LET) threshold of SEU, as compared with increasing the gate length. A new parameter, unit gate area LET threshold, is introduced for characterizing the change in efficiency of improving the SEU resistance with increasing the gate length and width of the transistors in a cell. The effect of decoupling capacitors on cell SEU LET threshold is also presented by making a comparison with that of the transistors with increased gate lengths.

The effect of statistical parameter distributions and stochastic ion strike locations in hardened memory arrays on observed SEU (single event upset) cross-section data is discussed. Application of numerical analysis to the parasitic bipolar gain distributions in SIMOX (separation by implantation of oxygen) SRAMs (static random-access memories) and the introduction of an effective critical charge based on sensitivities to ion strike locations explain the nonsaturating behavior of measured cross-section curves in SOI (silicon-on-insulator) and other hardened memories. A direct, analytical relationship between the measured cross-section curves seen in contemporary SOI CMOS SRAMs and the distribution of the parasitic bipolar beta values controlling each cell critical charge is presented. Results of this technique clearly indicate that distributed processing parameters and random ion strike locations lead to nonideal cross-section curves. The results also indicate that if the distribution for a critical parameter is known, the LET (linear energy transfer) threshold and shape of the upset cross-section curves can be anticipated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256 K SOI (silicon on insulator) SRAM that has attractive performance characteristics over the military temperature range of -55 to +125 degrees C. These include worst-case access time of 40 ns with an active power of only 150 mW at 25 MHz, and a worst-case minimum WRITE pulse width of 20 ns. Measured SEU performance gives an Adams 10% worst-case error rate of 3.4*10/sup -11/ errors/bit-day using the CRUP code with a conservative first-upset LET threshold. Modeling does show that higher bipolar gain than that measured on a sample from the SRAM lot would produce a lower error rate. Measurements show the worst-case supply voltage for SEU to be 5.5 V. Analysis has shown this to be primarily caused by the drain voltage dependence of the beta of the SOI parasitic bipolar transistor. Based on this, SEU experiments with SOI devices should include measurements as a function of supply voltage, rather than the traditional 4.5 V, to determine the worst-case condition. >

Single event upset (SEU) susceptibility due to high-energy ion hits on static RAM (SRAM) cells and various latch designs is evaluated using the two-dimensional circuit/transport SIFCOD code. Typical simulations involve as many as seven transistors, simultaneously solved using finite difference techniques on a high speed computer. Areas of SEU-susceptibility are identified on both the SRAM and latch designs. Experimental agreement for SRAM is achieved only with a parameter adjustment due to a 2D-3D effect. This parameter does not scale with device size as expected from physical models.