Single-Event Upset Prediction in SRAMs Account for On-Transistor Sensitive Volume

Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

By using the pulsed laser single effect facility, the single event upset and latch-up phenomenon are studied, and the bitmap of 90 nm complementary metal oxide semiconductor (CMOS) static random-access memory (SRAM) is mapped. It is shown that many multiple bit upsets occur and pulsed supply current of 20 mA amplitude is monitored. Based on the technology computer aided design (TCAD), it is found that the localized latch-up in CMOS SRAM is the main reason for the single event multiple bit upsets. Finally, by analyzing the results of the pulsed laser experiment and TCAD, it is found that the P/N well potential collapse is the key physical mechanism responsible for the spreading of the single event latch-up effect in 90 nm CMOS SRAM.

The impacts of the gate length and width of the transistors on the single event upset (SEU) hardness of static random access memory (SRAM) cells has been investigated by SPICE simulations, biased on a partially depleted (PD) silicon-on-insulator (SOI) CMOS technology. The results show that increasing the gate width can dramatically enhance the linear energy transfer (LET) threshold of SEU, as compared with increasing the gate length. A new parameter, unit gate area LET threshold, is introduced for characterizing the change in efficiency of improving the SEU resistance with increasing the gate length and width of the transistors in a cell. The effect of decoupling capacitors on cell SEU LET threshold is also presented by making a comparison with that of the transistors with increased gate lengths.

-As the demand for low-power, high-performance memory systems grows, the design of efficient SRAM (Static Random Access Memory) cells becomes increasingly crucial. This paper explores the power consumption, performance, and stability of two SRAM cell designs: the conventional 6T and the Single Ended 6T SRAM. While the conventional 6T SRAM is prone to read disturb noise and high leakage power, it remains widely used due to its simplicity and compactness. To address these issues, the Single Ended 6T SRAM cell is introduced as an alternative, which reduces both power consumption and area while maintaining competitive performance. The study provides a detailed analysis of static and dynamic power consumption, read/write stability, and overall energy efficiency for both cell architectures. Simulation results show that the Single Ended 6T SRAM offers significant improvements in power reduction without compromising speed, making it a promising solution for future low-power, high-performance memory applications. Keywords— SRAM cell, Pre-Charge Circuits, Sense Amplifiers, and Single-Ended vs. Conventional 6T SRAM Cell.

In modern technology era, the demand for Static Random Access Memory (SRAM) cells has been greatly increased due to its wide variety of applications. Power consumption, speed, read stability and leakage issues are the major design challenges related to SRAM. This paper presents a novel SRAM cell based on Multiple Supply Voltages and non-precharged RBL (MS-N10T) and also shows the comparison of various SRAM cells based on lector, sleep transistors and Transmission gate (TG) to reduce the power consumption when compared to LP10T. The SRAM cell MS-N10T when used in combination of TG and sleep transistors (TGNS-13T) further reduces the power consumption. The analysis further shows that the SRAM, TGNS13T reduces the power consumption approximately by 70-80%. On the Other hand, the LC14T SRAM cell enhances the stability approximately by 80-85%. The major objective of this work is to reduce the power consumption with marginal increase in propagation delay and to improve read stability so as to meet the challenges of advancements in technologies. All the various SRAM architectures are implemented using Cadence 45nm CMOS technology.  Â

This research paper proposes a low-power, high-stability 8T static random access memory (SRAM) cell. The proposed SRAM cell is a modified structure of the conventional 6T SRAM cell. The introduction of two diode-connected transistors in the pull-down network of the conventional 6T SRAM cell gives the proposed 8T SRAM cell structure. The presence of diode-connected transistors improves the power and noise performances of the proposed cell as compared to those of the conventional bit cells. The power consumption and static noise margin (SNM) of the suggested SRAM cell are calculated for write, hold and read operations. Also, the write and read delays of the proposed and conventional bit cells are observed. The power, speed, noise margin and area of the proposed 8T SRAM cell are compared with those of some of the existing SRAM cells. In comparison to conventional SRAM cells, the proposed cell consumes less power and has higher stability, according to the study. A novel dual-supply ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V or 200[Formula: see text]mV) concept is applied for the existing and proposed SRAM cells. The noise and power performances of SRAM cells are well improved under the condition of dual supply as compared to the conventional supply voltage ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V). A [Formula: see text] memory array of the proposed 8T SRAM cell is formed and the performance of the array structure is compared with that of [Formula: see text] array of the conventional 6T SRAM cell. The layouts of existing and proposed SRAM cells are illustrated. The simulation is carried out using the Cadence Virtuoso simulation EDA tool in 90-nm CMOS technology.

A low power CMOS Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGA) architecture is being presented in this paper. The architecture presented here is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. This architecture employs the fast and low-power SRAM blocks that are based on 10T SRAM cells. These blocks are employed in fast access of the configuration bits by using the shadow SRAM technique. The dynamic reconfiguration delay is being hidden behind the computation delay through the use of shadow SRAM cells. The combined effect of both the SRAM memory cells and the shadow SRAM scheme enables to support in reducing the delay and also to achieve reduced power consumption. Experimental results show reduced delay of about 8.035ns and power consumption of about 0.015W for the 10T SRAM memory cell with an overhead in area, relative to 4T and 6T SRAM cells. Also, the experimental results include the values of delay of about 8.979ns and power consumption of about 0.052W, achieved for the LB of FPGA architecture which employs CMOS SRAMs using the 10T SRAM memory cells in it.

The correlations between static noise margin (SNM) and single-event-upset (SEU) hardness for static random access memory (SRAM) cells are investigated in detail by comparing the values of the SNM with corresponding SEU thresholds of the SRAM cell for the different width values of the transistors of the cell, based on SPICE simulations. The results show that there is a positive correlation between the SNM and the SEU hardness of the cell, when the change for the widths of the two p-channel transistors is the same. At the same time, the results also reveal that a negative correlation exists between the SNM and SEU hardness of the cell, when the widths of the two n-channel transistors have the same change, and the width of the p-channel transistor is kept constant. In addition, it is also found that the cell SEU hardness is much more sensitive to the change of the width of the p-channel transistors than that of the n-channel ones, and the change in the width of the p-channel transistors is dominant in affecting the SNM, compared to that in the n-channel transistors, and hence the correlations between the SNM and SEU hardness.

As is known in the art, it is relatively difficult to write a logic ‘1’ to the five-transistor (5T) static random access memory (SRAM) cell if the SRAM cell currently stores a logic ‘0’. In this paper, we proposed a 5T SRAM cell and a cell voltage control circuit coupled to provide power to the SRAM cell. The cell voltage control circuit supplies the SRAM cell with the HVDD supply voltage if the SRAM cell is in a read mode. If the SRAM cell is being written or during a standby mode, the cell voltage control circuit supplies the SRAM cell with the LVDD supply voltage that is less than the HVDD supply voltage. Several HSPICE simulations show that the proposed SRAM cell provides an improvement in SRAM cell topology by providing an efficient solution to the write ‘1’ issue.

Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time ( ${T_{\mathrm{RA}}}$ ), and write access time ( ${T_{\mathrm{ WA}}} $ ) are also presented. The proposed cell achieves ${1.12{\times } /{\mathrm{ 1}}.{\mathrm{ 43}}{\times } /{\mathrm{ 5}}.{\mathrm{ 62}}\times } $ improvement in ${T_{\mathrm {RA}}}$ compared to TG8T/D6T/SE8T at a penalty of $ {1.1{\times } /{4}.{88}\times }$ in $ {T_{\mathrm{ WA}}} $ compared to D6T/TG8T and $ {1.19{\times } /1.18\times } $ in read/write power consumption compared to D6T. An improvement of $ {\rm 1.{\mathrm{ 12}}{\times } /{\mathrm{ 2}}.{\mathrm{ 15}}\times } $ in RSNM is observed compared to D6T/TG8T. The proposed cell consumes $ {5.38\times } $ less power during hold mode and also shows ${2.33\times } $ narrower spread in hold power @ $ {V_{\mathrm{ DD}} = 0.{\mathrm{ 4}}}$ V compared to D6T SRAM cell.

In this paper, we propose a radiation-tolerant by design 12 transistor (RTBD 12T) based Static Random Access Memory (SRAM) cell for deep space application. The designed SRAM cell can effectively tolerate radiation events. It exhibits high resilience towards radiation upsets and accordingly three out of four nodes of the cell are fully immune to radiation upsets, and it has a critical charge (QC) equal to 1.6 fC making it a more promising choice for deep space application. The design metrics of the proposed SRAM cell are compared with a few conventionally used SRAM cells like 6T, Quad node (QUATRO 10T) SRAM, Quadruple cross coupled storage cells (QUCCE 12T) and Writability Enhanced (WEQUATRO). The higher read stability is validated by the read static noise margin (RSNM) analysis in which the proposed cell achieves higher noise margin as compared to other SRAM cells. The proposed 12TSRAM cell exhibits improved results in terms of hold power, which is $\left( {0.86 \times } \right),\left( {0.40 \times } \right)$ and $\left( {0.74 \times } \right)$ compared to that of QUATRO 10T, QUCCE 12T and WEQUATRO, respectively.

This article presents a comprehensive assessment on the 6T static random access memory (SRAM) cell with 7-nm FinFET technology by implementing quantum physics-based device-circuit cooptimization. Seven key device design parameters and their multiple impacts on a 6T SRAM cell are systematically evaluated, focusing on materials band engineering, device design, circuit parameters tradeoff, and variation control. The area of SRAM cell under the same Fin quantization scheme remains constant in all evaluations. To the best of our knowledge, the most comprehensive discussion about circuit optimization from multiple device design parameters perspective is presented. Based on our cooptimization scheme, a SRAM cell is effectively designed. For a low-power and robust SRAM cell design, we achieve 56.7% reduction in leakage, 7.9% improvement in hold noise margin (HNM), 8.6% improvement in read noise margin (RNM), and 10.8% improvement in write margin (WM) at the expense of 19.3% increase in delay under design space of gate length (Lg) and spacer thickness (TSPC). For a high-speed SRAM cell design, we recommend focusing on the optimization of architecture and peripheral circuits. This framework not only has the advantages of easy implementation, technology-friendly, and high accuracy, but also suitable for path-finding researches on 5-nm node and beyond.

In this paper, the static noise margin (SNM) of FinFET static random access memory (SRAM) cells operating in the subthreshold region was investigated using an analytical solution of 3-D Poisson's equation. An analytical SNM model for subthreshold FinFET SRAM was demonstrated and validated by 3-D technology computer-aided design (TCAD) mixed-mode simulations. When compared with bulk SRAM, the standard 6T FinFET cell showed larger nominal READ SNM (RSNM), better variability immunity, and lesser temperature sensitivity of cell stability. Furthermore, examination of the stabilities of several novel independently controlled gate FinFET SRAM cells by using the proposed SNM model showed significant nominal RSNM improvements in these novel cells. However, the write ability is found to be degraded, which thus becomes an important concern for certain configurations in the subthreshold region. The result obtained indicates that the READ/WRITE word line voltage control technique is more effective than transistor sizing in improving the stability and write ability of the FinFET subthreshold SRAM. Furthermore, the impacts of process-induced variations on cell stability were also assessed. When compared with RSNM, it was found that WRITE SNM is more susceptible to process variations. While 6T is not a viable candidate for subthreshold SRAM, and 8T/10T cells must be used in bulk CMOS, the present analysis established the potential of 6T FinFET cells for subthreshold SRAM applications.

The growing demand for low-power static random access memory (SRAM) cells in Internet of Things (IoT) devices has led to the development of various SRAM cell topologies that minimize power consumption while maintaining performance and stability. In this paper, we have analyzed various SRAM designs based on different parameters, such as power dissipation, delay, area, energy, and stability. It is observed that 6T SRAM cell, consisting of six transistors, is the most widely used topology due to its simplicity and low area requirements. However, larger cells such as 8T,9T, and 10T have been developed to improve stability and reduce power consumption, although they require more area. It has been observed8 T work better for read delay while 9T works better for 9 Scaling down SRAM cells to smaller feature sizes presents challenges in maintaining stability and reliability while minimizing power consumption.

Heavy ion-induced single event upsets (SEUs) of static random access memory (SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross sections and multiple cell upset (MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions. In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers (LETs). The average percentage of MCUs of 3D SRAM increases from 17.2 to 32.95%, followed by the energy of 209Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-to-face structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross sections of planar SRAM with experimental data. The upset cross sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields.