Physics-Based Device-Circuit Cooptimization Scheme for 7-nm Technology Node SRAM Design and Beyond

-As the demand for low-power, high-performance memory systems grows, the design of efficient SRAM (Static Random Access Memory) cells becomes increasingly crucial. This paper explores the power consumption, performance, and stability of two SRAM cell designs: the conventional 6T and the Single Ended 6T SRAM. While the conventional 6T SRAM is prone to read disturb noise and high leakage power, it remains widely used due to its simplicity and compactness. To address these issues, the Single Ended 6T SRAM cell is introduced as an alternative, which reduces both power consumption and area while maintaining competitive performance. The study provides a detailed analysis of static and dynamic power consumption, read/write stability, and overall energy efficiency for both cell architectures. Simulation results show that the Single Ended 6T SRAM offers significant improvements in power reduction without compromising speed, making it a promising solution for future low-power, high-performance memory applications. Keywords— SRAM cell, Pre-Charge Circuits, Sense Amplifiers, and Single-Ended vs. Conventional 6T SRAM Cell.

This research paper proposes a low-power, high-stability 8T static random access memory (SRAM) cell. The proposed SRAM cell is a modified structure of the conventional 6T SRAM cell. The introduction of two diode-connected transistors in the pull-down network of the conventional 6T SRAM cell gives the proposed 8T SRAM cell structure. The presence of diode-connected transistors improves the power and noise performances of the proposed cell as compared to those of the conventional bit cells. The power consumption and static noise margin (SNM) of the suggested SRAM cell are calculated for write, hold and read operations. Also, the write and read delays of the proposed and conventional bit cells are observed. The power, speed, noise margin and area of the proposed 8T SRAM cell are compared with those of some of the existing SRAM cells. In comparison to conventional SRAM cells, the proposed cell consumes less power and has higher stability, according to the study. A novel dual-supply ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V or 200[Formula: see text]mV) concept is applied for the existing and proposed SRAM cells. The noise and power performances of SRAM cells are well improved under the condition of dual supply as compared to the conventional supply voltage ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V). A [Formula: see text] memory array of the proposed 8T SRAM cell is formed and the performance of the array structure is compared with that of [Formula: see text] array of the conventional 6T SRAM cell. The layouts of existing and proposed SRAM cells are illustrated. The simulation is carried out using the Cadence Virtuoso simulation EDA tool in 90-nm CMOS technology.

Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode

The growing demand for low-power static random access memory (SRAM) cells in Internet of Things (IoT) devices has led to the development of various SRAM cell topologies that minimize power consumption while maintaining performance and stability. In this paper, we have analyzed various SRAM designs based on different parameters, such as power dissipation, delay, area, energy, and stability. It is observed that 6T SRAM cell, consisting of six transistors, is the most widely used topology due to its simplicity and low area requirements. However, larger cells such as 8T,9T, and 10T have been developed to improve stability and reduce power consumption, although they require more area. It has been observed8 T work better for read delay while 9T works better for 9 Scaling down SRAM cells to smaller feature sizes presents challenges in maintaining stability and reliability while minimizing power consumption.

Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time ( ${T_{\mathrm{RA}}}$ ), and write access time ( ${T_{\mathrm{ WA}}} $ ) are also presented. The proposed cell achieves ${1.12{\times } /{\mathrm{ 1}}.{\mathrm{ 43}}{\times } /{\mathrm{ 5}}.{\mathrm{ 62}}\times } $ improvement in ${T_{\mathrm {RA}}}$ compared to TG8T/D6T/SE8T at a penalty of $ {1.1{\times } /{4}.{88}\times }$ in $ {T_{\mathrm{ WA}}} $ compared to D6T/TG8T and $ {1.19{\times } /1.18\times } $ in read/write power consumption compared to D6T. An improvement of $ {\rm 1.{\mathrm{ 12}}{\times } /{\mathrm{ 2}}.{\mathrm{ 15}}\times } $ in RSNM is observed compared to D6T/TG8T. The proposed cell consumes $ {5.38\times } $ less power during hold mode and also shows ${2.33\times } $ narrower spread in hold power @ $ {V_{\mathrm{ DD}} = 0.{\mathrm{ 4}}}$ V compared to D6T SRAM cell.

We present a hybrid nanoelectromechanical (NEM)/CMOS static random access memory (SRAM) cell, in which the two pull-down transistors of a conventional CMOS six transistor (6T) SRAM cell are replaced with NEM relays. This SRAM cell utilizes the infinite subthreshold slope and hysteretic properties of NEM relays to dramatically increase the cell stability compared to the conventional CMOS 6T SRAM cells. It also utilizes the zero off-state leakage of NEM relays to significantly decrease static power dissipation. The structure is designed so that the relatively long mechanical delay of the NEM relays does not result in performance degradation. Circuit simulations are performed using a VerilogA model of a NEM relay. Compared to a 65nm CMOS 6T SRAM cell, when 10nm-gap NEM relays (pull-in voltage = 0.8V, pull-out voltage = 0.2V, on resistance = 1ki2) are integrated, hold and read static noise margin (SNM) improve by ~110% and ~250%, respectively. In addition, static power dissipation decreases by ~85%. The write delay decreases by ~60%, while read delay decreases by ~10%. The advantages in SNM and static power dissipation are expected to increase with scaling.

A low power CMOS Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGA) architecture is being presented in this paper. The architecture presented here is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. This architecture employs the fast and low-power SRAM blocks that are based on 10T SRAM cells. These blocks are employed in fast access of the configuration bits by using the shadow SRAM technique. The dynamic reconfiguration delay is being hidden behind the computation delay through the use of shadow SRAM cells. The combined effect of both the SRAM memory cells and the shadow SRAM scheme enables to support in reducing the delay and also to achieve reduced power consumption. Experimental results show reduced delay of about 8.035ns and power consumption of about 0.015W for the 10T SRAM memory cell with an overhead in area, relative to 4T and 6T SRAM cells. Also, the experimental results include the values of delay of about 8.979ns and power consumption of about 0.052W, achieved for the LB of FPGA architecture which employs CMOS SRAMs using the 10T SRAM memory cells in it.

As is known in the art, it is relatively difficult to write a logic ‘1’ to the five-transistor (5T) static random access memory (SRAM) cell if the SRAM cell currently stores a logic ‘0’. In this paper, we proposed a 5T SRAM cell and a cell voltage control circuit coupled to provide power to the SRAM cell. The cell voltage control circuit supplies the SRAM cell with the HVDD supply voltage if the SRAM cell is in a read mode. If the SRAM cell is being written or during a standby mode, the cell voltage control circuit supplies the SRAM cell with the LVDD supply voltage that is less than the HVDD supply voltage. Several HSPICE simulations show that the proposed SRAM cell provides an improvement in SRAM cell topology by providing an efficient solution to the write ‘1’ issue.

As CMOS devices near the nanometer regime, scaling them down has a number of repercussions, such as short channel effects and process fluctuations, which degrade the device's reliability and performance. FinFET is one of the promising ones for overcoming this problem, according to researchers, because it has better channel management and lower overall capacitance, the 6T Static Random Access Memory (SRAM) circuit design will perform better. This research study evaluates 6T and 9T SRAM cells created with CMOS and FinFET by utilizing 22nm technology and further these SRAM cells are compared based on numerous performance characteristics such as write delay, read delay, static power and static noise margin (SNM). The Predictive Technology Models (PTM) files are used to simulate the 22nm CMOS and FinFET based SRAM cells which are developed by Arizona State University in the Cadence Virtuoso tool.

SRAM (Static Random Access Memory) has become a major key component in many VLSI Chips, due to its high storage density and quick access time, it has become a popular data storage device. SRAM has played a significant role in the global VLSI sector. Due to the significant increase of low power and low voltage memory systems in recent times, SRAM has been prioritised in the research sector. This is owing to the increased demand for high-end devices, IC memory cards, and other communication devices, as well as the advancement of portable battery-operated devices. The power and area of a low-power 6T SRAM cell design are assessed in this research. This work describes the design and implementation of a 6T SRAM cell in standard CMOS process technology at 180nm, 90nm and 45nm nodes. In the Cadence Virtuoso Software, this simulation was run. The Static Noise Margin has been used to analyse the performance of SRAM cells. The schematic, transient simulation, and DC analysis are all included in this work.

In modern technology era, the demand for Static Random Access Memory (SRAM) cells has been greatly increased due to its wide variety of applications. Power consumption, speed, read stability and leakage issues are the major design challenges related to SRAM. This paper presents a novel SRAM cell based on Multiple Supply Voltages and non-precharged RBL (MS-N10T) and also shows the comparison of various SRAM cells based on lector, sleep transistors and Transmission gate (TG) to reduce the power consumption when compared to LP10T. The SRAM cell MS-N10T when used in combination of TG and sleep transistors (TGNS-13T) further reduces the power consumption. The analysis further shows that the SRAM, TGNS13T reduces the power consumption approximately by 70-80%. On the Other hand, the LC14T SRAM cell enhances the stability approximately by 80-85%. The major objective of this work is to reduce the power consumption with marginal increase in propagation delay and to improve read stability so as to meet the challenges of advancements in technologies. All the various SRAM architectures are implemented using Cadence 45nm CMOS technology.  Â

In this paper, we propose a new design of high‐performance ultralow power carbon nanotube field effect transistor (CNTFET)‐based nine‐transistor static random access memory (SRAM) cell and its implementation using shared bitline (BL) and half‐select free techniques. Simulations of the 9T SRAM design, using CNTFET compact model, have presented merits over the silicon‐complementary‐metal oxide semiconductor (CMOS) SRAM cell in terms of leakage current, power consumption, and stability. Uses of the half‐select free technique eliminate the conflict between read and write operations and shared BL technique offers reduced physical layout area and enhanced data access speed. Further, uses of the increased number of tubes or say CNT array in the CNTFET device increases the probability of functionality (>95%) with a high yield SRAM cell.

One of the significant components of semiconductor integrated circuits is memories. The 6T static random access memory (SRAM) is a basic building block in digital memory systems, commonly used in many applications because of its efficiency and speed. SRAM is a key element in contemporary digital systems, where performance, power consumption and stability are crucial parameters. The 6T SRAM structure is extensively utilised because of its trade-off between read stability, write performance and low power usage. This paper’s main focus is on analysing the performance of 6T SRAM cells using 45 nm CMOS technology. This study does a comprehensive analysis of the SRAM cell’s total DC power and latency. The 45 nm technology node Cadence Virtuoso tool is used to report simulation results.

In this paper, we propose a radiation-tolerant by design 12 transistor (RTBD 12T) based Static Random Access Memory (SRAM) cell for deep space application. The designed SRAM cell can effectively tolerate radiation events. It exhibits high resilience towards radiation upsets and accordingly three out of four nodes of the cell are fully immune to radiation upsets, and it has a critical charge (QC) equal to 1.6 fC making it a more promising choice for deep space application. The design metrics of the proposed SRAM cell are compared with a few conventionally used SRAM cells like 6T, Quad node (QUATRO 10T) SRAM, Quadruple cross coupled storage cells (QUCCE 12T) and Writability Enhanced (WEQUATRO). The higher read stability is validated by the read static noise margin (RSNM) analysis in which the proposed cell achieves higher noise margin as compared to other SRAM cells. The proposed 12TSRAM cell exhibits improved results in terms of hold power, which is $\left( {0.86 \times } \right),\left( {0.40 \times } \right)$ and $\left( {0.74 \times } \right)$ compared to that of QUATRO 10T, QUCCE 12T and WEQUATRO, respectively.