Hybrid Substrate With Ultralarge Organic Interposer for Heterogeneous Integration

The fan-out panel-level chip-last packaging for heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, and fabrication of: (a) the heterogeneous integration of one large chip and one small chip with 50µm-pitch (minimum), (b) a fine metal linewidth (L) and spacing (S) redistribution-layer (RDL)-first substrate on a temporary glass carrier, (c) an ordinary build-up package substrate on a panel, (d) a hybrid substrate which is by soldering the RDL-substrate on top of the build-up substrate, and (e) the chips to hybrid substrate bonding and underfilling. Reliability assessment by thermomechanical simulation includes thermal cycling of the heterogeneous integration of the two-chip package on the hybrid substrate that is performed by a nonlinear temperature- and time-dependent finite-element analysis.

In this study, the reliability of chiplets heterogeneous integration on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the thermal cycling test and drop test of the structure. The test results are plotted into Weibull distributions, where the Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope interval and the true characteristic life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the chip/package assembly of the heterogeneous integration package are provided and discussed.

The fan-out chip-last panel-level packaging for chiplets heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, and fabrication of a high-density organic hybrid substrate using an interconnect-layer.

Future high-performance large-scale digital systems will increasingly require high-density multichip hybrid packaging techniques. Chip attachment by flip-chip mounting, as in the well-established eontrolled-collapse solder-bump contact approach, has several fundamental advantages over the more familiar wire-bonded hybrid assembly approach. However, testing of flip-chip mounted assemblies and replacement of defective parts, along with the alignment of chip bonding pads to substrate pads, involves substantial practical difficulties. A chip alignment template, aligned to and permanently mounted on the hybrid substrate, is proposed. Anisotropic etching of silicon wafers provides a high-precision technique compatible with batch fabrication of the templates. Fabrication of such templates and factors influencing chip alignment accuracy are discussed.

In this study, the heterogeneous integration of two chips on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the materials, design, process, fabrication, and reliability of the package. Drop test and results of the package are also provided.

As the industry moves forward the age of more than Moore, the next generation of packaging moves forward high density of chiplet or die splitting package integration. Especially for high performance computing applications, the advance packaging is to provide the economic benefits to integrate multiple chiplet dies by silicon or organic interposer. Organic interposer is one of the alternative interface for die to die interconnection. It is well-known by FO-MCM to apply in chiplets integration and ASIC to Serdes dies integration by the homogeneous package integration concept. Due to the motivation of AI computing and HPC market growth, the trend is formed to integrate the packaged HBM into packaging module as the heterogeneous integration package (HIP). Both of the platforms, 2.5D with silicon interposer base and FO-EB with partial bridge die as interconnection media, have already launched to market in recent years. FO-MCM with purely organic interposer, is also discussed to implement into the heterogeneous integration field. The fully organic interposer can provide the flexible design in multiple RDL layers and line / space for HPC products. In this study, it is to address FO-MCM platform with purely organic interposer to implement heterogeneous packaging with integrated HBMs. Chip last approach in FO-MCM has the advantage to control RDL quality and take “known-good RDL” for top die cost rescuing. The fan-out RDL configuration is 4 layers with min, L/S of 2/2um. In the verification processes, based on the simulation analysis, the warpage and stress are optimized by material and under-fill selections in this discussion. The assembly results indicated the warpage and reliability validation passed by MSL4, TCT700x, uHAST96, and HTST1000hrs conditions.

In this study, the recent advances and trends in multiple system and heterogeneous integration with through-silicon via (TSV)-less interposer (organic interposer or 2.3-D IC integration) will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of multiple system and heterogeneous integration with TSV-less interposer. Also, some recommendations of 2.3-D IC integration will be provided.

In recent year, based on high performance computing (HPC) and big data computing (BDC) application need to upgrade these performance incudes high process rates, high communication rate and low latencies. As transistor scaling reaches physical and economic barriers, the performance and cost of transistors are increasingly lagging behind the historical Moore's Law trajectory. Heterogeneous integration of SiP (system in package), 2.5D and fan-out solutions are driving the beyond Moore vision. In this paper, it is demonstrated that one of fan-out technology is to provide the high RDL layer count and fine RDL line width and line space, called FO-MCM (fan-out multi-chip modules). The FOMCM used organic interposer is applied lower RC delay and the high I/O density interconnection for HBM dies integration in comparison to 2.5D with the whole piece of Si interposer. Since HPC and BDC application performance derived High Bandwidth Memory grow up, that also impact the assembly package structure in parallel. The next general HBM need more metal layers to keep the performance in high frequency compare to original package design. SPIL's FO-MCM development integrates chips by 1 ASIC die and 2 HBM with 4–6 layers RDL show in Fig. 1. Since FOMCM used organic interposer to bridge chips, this kind of package can provide the solution which is cheaper than 2.5D and has simply vendor management to the end customer. As such, an overview of Fan-out integration solution associated with HBM will be presented in this paper.

Package on Package (PoP) technology can play a vital role in advanced packaging for various reasons. The use of a thin interposer allows for tighter wiring ground rules and can reduce die-to-die latency when placing either multiple die on a single interposer or placing multiple interposers on a larger carrier laminate. This assembly technology can also be of benefit for heterogeneous integration applications. The main challenge for bond and assembly process development with organic to silicon bonding, particularly with thin organic interposers, is to overcome solder join defects (non-wets, bridges) created by highly warped components. To address this issue, two different assembly process flows were developed, namely process A (chip first) and process B (laminate first) with PoP type test vehicle hardware. The assembly was composed of a 23×29mm die with 185μm pitch SAC solder connected to an organic interposer of 37.5×37.5mm dimension and 0.7mm thickness. The bottom side of the interposer, with either CuOSP or NiPdAu pads, was soldered to a 68.5×68.5mm carrier laminate of 1.8mm thickness and CuOSP pads with SAC 305 μBGA solder balls of 0.4mm pitch. To ensure bond and assembly integrity, over 30 cross-sections were performed on the modules from these two process sequences. μBGA's were of first interest as warpage issues forced a thorough optimisation of joining parameters. Microstructure appears with undeniable variations between process sequences and interposer pad surface finishes. Cross-polarized microscopy observation and etching of cross-sections, with over 2500 μBGA characterized, showed that process flow A microstructure was mostly constituted by very large and few grains of beta-Sn phase compared to mainly small interlaced grains for process flow B. IMC's with "chip first" (process flow A) assembly were composed of rare AgSn crystals and several CuSn filaments, which were also observed on "laminate first" (process flow B), but only with NiPdAu interposer pads. Also, for process sequence B with NiPdAu pads, thick plates of AgSn were observed, as opposed to very thin sheets with CuOSP pads. Interim cross-section in the bond and assembly process flows allowed the formulation and verification of a hypothesis on the mechanism that leads to a "laminate first" atypical microstructure. Cooling rates during reflow and interposer pad surface finish will change all the kinetics of intermetallic nucleation and produce eccentric growth. A thorough mechanism understanding will allow a proper process parameter intervention to modulate a desired microstructure from a reliability stand point.

As silicon scaling closer to physical limit, future reduction of the gate oxide does not lower down the cost per transistor. But the demand of higher functionality and lower cost of electronic devices do not slow down. Development of electronic devices metaphor to high-density package integration. What the electronic industries do is to break down a large die to a chiplet-based devices for improving yield and lower the total cost. Chiplet package become a key technology to continue Moore's law. With the intensive researches, multiple chiplet packages are evolved such as multi chips on Si interposer using TSV (2.5D), die to die stack on each other (3D), Fan-Out Multi Chip Module (FOMCM), and EMIB (Embedded Multi-Die Interconnect Bridge). These packages are developed for the server, high performance computing, router, and switcher markets. But, the integration of high bandwidth memory devices and multiple ASIC dies together requires very high I/O counts and signal transmitting. Thus, a much higher RDL (Redistribution Layer) layer counts, finer bump pitch and smaller line- space (L/S) are designed. Each of these chiplets has its limitations. Large 2.5D package has its cost concerns on large Si interposer and mismatch of the Si interposer with substrate on reliability test. Whereas, large FO-MCM technology is limited by finer L/S and higher layers count of RDL. Presently, the package is heading the bottleneck at 1/1 μm L/S, 5 layers RDL and 2 reticle size chip module. As for EMIB technology, it is constrained by L/S that could only down to 5/5 μm. In this paper, we have successfully developed a scalable chiplet package technology, namely Fan-Out Embedded Bridge (FOEB). This chiplet package enables near monolithic short reach BEOL connections between dies. FOEB can have multiple RDL layers and Si bridge that has much finer L/S for interconnection. In addition to, multiple dies can be bridged together into one single chip module. In this paper, the demonstration of FOEB test vehicle, which integrate chips by 1 ASIC die and 4 memory dies (1+4) with 4 embedded bridge dies on mold-based interposer, 3 layers of RDL are presented. By comparing packages using FOMCM and 2.5D to fabricate. FOEB package has much lower warpage and 2× lower stress value as compare to 2.5D. But similar to FOMCM. Owing to this reason, the FOEB chiplet package were tested 2x longer temperature cycle with condition-G without single failure as compared to 2.5D. The assembly yield of FOEB is comparable to FOMCM. And much higher than that of EMIB. Assembly of FOEB chiplet package adopts organic interposer. The wafer warpage changes from concave to convex shape after die attachment on the molded interposer. This limits some of the machines handling and induces wafer cracking. By properly select the right molding compound, and glass carrier CTE, we have successfully developed this FOEB chiplet and validated through reliability test. This chiplet allows us to scale the package to much higher I/O density, finer L/S, higher RDL layers, and number of dies that can be integrated into one single chip module.

This paper presents an innovative additive manufacturing approach leveraging an organic interposer for low-parasitic and low-loss heterogeneous integration of monolithic microwave integrated circuits (MMICs) at RF and millimeter-wave (mm-wave) frequencies. The methodology involves precise fabrication of patterned cavities within the interposer to seamlessly embed MMICs. Conductive inks, micro-dispensed and cured to form lateral interconnections and integrated chip carriers, are further refined by pico-second pulsed laser micromachining to achieve micrometer-scale accuracy. This laser refinement significantly improves reflection coefficients, facilitating wideband impedance matching. Experimental validation through simulation and measurement of S-parameters for an embedded MMIC distributed amplifier demonstrates superior performance as compared to traditional wire-bonded quad flat no-lead (QFN) packages, with low interconnect attenuation (0.028 dB/mm at 5 GHz, 0.187 dB/mm at 20 GHz, and 0.512 dB/mm at 30 GHz). A system-in-package (SiP) protoype, comprising a cascaded MMIC amplifier and filter as a receiver module, achieved return losses below 10 dB and low package loss. Enhanced laser trimming and de-embedding techniques further reduced return losses beyond 27 dB and decreased insertion losses by 0.5-0.8 dB up to 30 GHz, significantly improving fabrication tolerance and performance consistency. Also, this study introduces and validates an equivalent circuit model for ground-signal-ground (GSG) probe pads up to 40 GHz repeatedly fabricated by laser-enhanced direct-print additive manufacturing (LE-DPAM) for several devices under test (DUTs). The findings offer critical insights for future development and verification of LE-DPAM foundry-compatible process design kits (PDKs), highlighting transformative potentials of additive manufacturing for advanced heterogeneous integration of MMICs, RFICs, and mixed-signal circuits.