Implementation of a new neurochip using stochastic logic

Uniform approximation and Bernstein polynomials with coefficients in the unit interval

Stochastic Satisfiability Modulo Theories (SSMT) [1] is a quantitative extension of classical Satisfiability Modulo Theories (SMT) inspired by stochastic logics. It extends SMT by the usual as well as randomized quantifiers, facilitating capture of stochastic game properties in the logic, like reachability analysis of hybrid-state Markov decision processes. Solving for SSMT formulae with quantification over finite and thus discrete domain has been addressed by Tino Teige et al. [2]. In this paper, we extend their work to SSMT over continuous quantifier domains (CSSMT) in order to enable capture of continuous disturbances and uncertainty in hybrid systems. We extend the semantics of SSMT and introduce a corresponding solving procedure. A simple case study is pursued to demonstrate applicability of our framework to reachability problems in hybrid systems.

This two-part paper reviews recent innovations in circuit design that have accelerated the miniaturization of sensor nodes. In this second part of the paper, we focus on key building blocks of miniaturized sensor nodes, such as data transceivers, energy harvesters, power management units, and digital logic circuits. System level design considerations are also discussed to provide guidelines for the design of a miniaturized system. As an example prototype design, a 2.7-cm3 global navigation satellite system (GNSS) logger is proposed. This paper includes a die-stacked sensor platform composed of an ARM cortex M0 processor, energy harvester, power management unit, solar cell, optical receiver, sensor layer, and RF transmitter that exploits the discussed design techniques for ultra-low power operation. The GNSS logger can store GNSS signals of >1 k positions on a single battery charging without additional energy harvesting.

In this paper we present a new approach to the formal specification of distributed real-time systems using the formal description technique LOTOS together with a stochastic temporal logic STL. This approach previously presented in the context of LOTOS/QTL, is characterized by a separation of concerns. The functional behaviour is described in LOTOS without regard for the time critical constraints. The specification is then extended with precise real-time requirements written in STL. We present a method to generate a timing event scheduler from the requirements in order to monitor the functional behaviour.

This paper primarily focuses on Gate Diffusion Input (GDI) technique used for the implementation of digital logic circuits. It also discusses in detail the limitations and modifications of the basic GDI technique. Initially, GDI was a new technique used for low power digital combinational circuit design. This approach provides a reduction in power consumption, propagation delay, and area of digital circuits while the logic design complexity is small. GDI methodology allows implementation of a wide range of complex logic functions using only two transistors. GDI is a new technique for digital circuits implementation with a lot of advantages over existing ones. This paper also analyzes the recent applications of GDI technique which are the implementation of MASH 1-1 and MOD 2 modulator for Sigma Delta DACs and development of full adders for efficient arithmetic operations.

In recent years, research into and development of hillside tractors has become a popular topic in the field of agricultural engineering in China. To solve the main problems associated with a low adjustment range of the working speed, complex operation, and low safety for slope operation of medium-sized crawler tractors, a hydrostatic drive system that can be used for hillside crawler tractors was designed. According to the operation requirements of a hillside crawler tractor, the parameters of the three-cylinder diesel engine, hydrostatic transmission (HST), drive rear axle, and other key components of the drive system were matched after the force and motion analyses of the tractor, and then the main performance indicators, including the traction performance, system pressure and working speed of the drive system were verified. On this basis, a drive system performance test bench was built, and the traction performance and starting acceleration performance of the drive system was tested. The results of the traction bench test show that when the engine was at the maximum torque point of 1700 r/min, the maximum theoretical tractive force outputted by the tractor in Gear I was 114,563 N, and the maximum theoretical tractive force outputted by tractor in Gear II was 10,959.2 N, which were both larger than the traction resistance of 9550.6 N experienced by the hillside tractor ploughing on the slope. The results of the initial acceleration bench test show that the tractor driving speed can gradually increase with increasing output of the variable pump and can reach the maximum in 3 s. When the tractor was driving on flat ground, the maximum driving speeds of Gear I, Gear II, and Gear III were 4.65 km/h, 6.58 km/h, and 8.57 km/h, respectively, which are close to the theoretical values. When the tractor was driving on a 15° slope, the maximum driving speeds of Gear I, Gear II, and Gear III were 4.55 km/h, 6.25 km/h, and 8.28 km/h, respectively. It can be concluded that the design matching of the drive system is reasonable, the speed consistency is good and there is enough power reserve, which can meet the requirements for a large workload.

Digital circuits are preferred over its analog counterpart with the invention of microprocessors, microcontrollers, digital signal processors and Field Programmable Gate Arrays (FPGA). Digital circuits in the form of digital arithmetic and digital logics are employed for various applications. On the other side, Support Vector Machine (SVM) is considered as a state-of-the-art tool for pattern recognition. In this paper, a novel attempt is made to study, assess and design digital circuits using two-class and multi class support vector machine classifiers. It is reported in literature that computational complexity and the classification time for SVM classifier depends on the number of support vectors required for classification. In order to reduce the number of support vectors, an optimum threshold technique based SVM classifier is employed for the design of digital circuits and it is observed that a maximum of 87.5% of total support vectors are pruned on using the technique.

The method which employs the frame accumulation and shaped function is effective in low-light-level imaging. However, it has drawbacks of lower imaging speed and complex operation. To optimize the method, we provide the design of an improved low-light-level imaging system with higher detection sensibility. The design is developed specifically for a faster imaging speed based on field programmable gate arrays. It features the use of least-square algorithm and a saw-tooth wave varied light applied to the image sensor. By manipulation of the video signal in synchronous dynamic random access memory, a low-light-level image which was previously undetectable can be estimated. The design simplifies the imaging process and doubles the imaging speed, and makes the system adapted to long range imaging.

Notice of Violation of IEEE Publication Principles “Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate” by Suhaib Ahmed and Syed Farah Naz in IEEE Transactions on Circuits and Systems II: Express Briefs After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE’s Publication Principles. This paper contains significant portions of original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. “Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata” By Haotian Chen, Hongjun Lv, Zhang Zhang, Xin Cheng and Guangjun Xie in Journal of Circuits, Systems, and Computers, Vol. 28, No. 8, 2017 The advantages such as high operating frequency (in the range of few THz), low power dissipation, small size and high density in the nano regime has led to the application of Quantum dot Cellular Automata (QCA) in designing various digital circuits. In this brief, an ultra-efficient two input XOR gate design in QCA is proposed. It is a single layer design consisting of only 9 cells with no crossover and operating on cell to cell interaction. The functionality of the proposed gate has been verified at both physical and simulation level. In addition to this, fault tolerance to single cell missing defect, single cell addition defect and single cell displacement defect of the proposed XOR gate has also been presented. Based on the performance evaluation, it is seen that the proposed XOR gate has least cell count, least area and least latency which in turn leads to least circuit cost. Also, the proposed design dissipates least energy. The applicability of proposed XOR gate has also been investigated by designing various cost efficient digital circuits such as full adder, parity checker, etc.

In this paper it is proposed the implementation in Matlab & Tools environment, by using Simulink and Simscape plug-ins, of empirical models of the Carbon Nanotube Field Effect Transistor (CNTFET) in order to evaluate the capability of this very interesting design and simulation environment to easily design the most advanced generation of digital electronic circuits. Empirical models of electronic devices are particularly suitable for the Computer Aided Design (CAD) of digital electronic circuits. They are generally very compact, fast and accurate, without any physical approximation, and then they can be easily implemented in circuit simulators. The paper aims at describing the core of a possible CAD tool for digital circuits using CNTFETs, designed by the author, and at evaluating its suitability and usefulness by design examples. Therefore, they have been implemented two models of CNTFETs in Matlab & Tools environment and it has been performed the design of basic digital logic gates and memory elements. One of the two models has been developed by the author and already validated. The other model has been developed by valuable authors at Standford University and is used for comparisons. Results show the great usefulness of the empirical approach and of the Matlab & Tools environment for the quick and easy design of digital electronic circuits using CNTFETs.

Logic gates form the basis of modern digital computers, and from a theoretical perspective they are the unit of computation since they are the fundamental discrete logic element. By creating circuits of interconnected logic gates, computers can calculate more complex operations, such as adders, multiplexers, flips-flops, and eventually processing and control units. Herein, we use a 3D-printed platform consisting of a rectangular 2D-array of interconnected cells containing the Belousov–Zhabotinsky (BZ) reaction. This reaction can be made to oscillate between two states to simulate the binary codification of digital electronics. Within the platform each cell contains a magnetic stirrer that can be individually stirred to control the local oscillations of the BZ reaction in that cell, but all the cells are also weakly interconnected through the common medium, and here we used the convolution of their individual oscillations to perform heterotic computations. Moreover, the 3D-printed vessel can be fabricated using different architectures, to for example define how the cells are connected, and thus controlling how the oscillations propagate between them. We took advantage of these features to simulate the ”AND”, ”OR, and ”XOR” logic gates. We also implemented a 2D Cellular Automata. To do so we defined the cells where the BZ reaction oscillates as “on”, and set the transition rule as the propagation of oscillations from the “on” cells towards “off” ones. These results pave the way towards the development of more sophisticated unconventional computers, which might potentially enhance future Artificial Life implementations more effectively than current silicon-based advancements.

Defects and faults arise from physical imperfections and noise susceptibility of the analog circuit components used to create digital circuits resulting in computational errors. A probabilistic computational model is needed to quantify and analyze the effect of noisy signals on computational accuracy in digital circuits. This model computes the reliability of digital circuits meaning that the inputs and outputs and their implemented logic function need to be calculated probabilistically. The purpose of this paper is to present a new architecture for designing noise-tolerant digital circuits. The approach we propose is to use a class of single-input, single-output circuits called Reliability Enhancement Network Chain (RENC). A RENC is a concatenation of n simple logic circuits called Reliability Enhancement Network (REN). Each REN can increase the reliability of a digital circuit to a higher level. Reliability of the circuit can approach any desirable level when a RENC composed of a sufficient number of RENs is employed. Moreover, the proposed approach is applicable to the design of any logic circuit implemented with any logic technology.

Thin and thick film materials are widely used in modern electronic circuits due to their ability to provide miniaturization, high performance, and cost-effective production. Thin film technology involves depositing layers of conductive, resistive, and dielectric materials onto a substrate, typically using methods like vacuum deposition or sputtering. Thick film technology, on the other hand, uses a screen-printing process to deposit paste-like materials onto substrates and is known for its durability and adaptability to harsh environments. Both technologies play crucial roles in designing analog and digital circuits, especially in fields like telecommunications, automotive electronics, and medical devices. The increasing demand for smaller, faster, and more efficient electronic devices has put pressure on the development of high-performance circuits using thin and thick film technologies. A key challenge is optimizing material properties to balance electrical performance, thermal management, and mechanical reliability in both analog and digital circuits. This study explores the design and performance evaluation of analog and digital circuits using thin and thick film materials. Thin film circuits were fabricated using sputtering techniques to deposit layers of resistive and conductive materials with precise thickness control. Thick film circuits were created by screen-printing conductive, resistive, and dielectric pastes onto ceramic substrates. Electrical performance was tested for both types of circuits, focusing on parameters such as resistance, capacitance, and inductance. The thin film circuits demonstrated superior electrical performance with lower parasitic inductance and capacitance, achieving a resistance tolerance of ±1% and a thermal coefficient of resistance (TCR) of ±50 ppm/°C. The thick film circuits, while having slightly higher parasitic values, offered robustness and mechanical stability in high-temperature environments, with TCR values ranging from ±100 to ±250 ppm/°C. Both technologies showed significant promise, with the choice of material depending on the specific application requirements for analog and digital systems.

Since the first electronic computer, ENIAC, was demonstrated in 1946, we human beings have been pursuing faster computers. Basic computer elements executing digital operation have been progressing continuously from the age of vacuum tubes. The basic elements have been changed to transistors, integrated circuits, and then large scale integrated circuits in this half century. During these periods, the operating speed of today’s computers has increased more than one billion times that of ENIAC. Some applications, such as weather forecasting, protein design, and astronomical simulation will never be satisfied by the speed of today’s computers. In the field of telecommunication, we also require very large scale routers with operation speed faster than 10 terra bits per second to deal with the huge amount of information on the Internet. Moreover, modern wireless communications requires wider and wider bandwidths in order to handle higher data rates and increase data capacity. This demands higher sample rate mixed signal circuits and higher clock rate digital signal processing circuits. In order to satisfy the need for higher speeds, researchers have been developing tiny transistors with shorter gate lengths; now they are developing transistors with twenty nanometer gate lengths. Many engineers fear, however, that the switching speed of transistors will saturate inthe near future. Thus, completely new switching elements, such as superconducting devices, single electron transistors, molecular devices, spin transistors, quantum devices and so forth, are now being investigated. Among them, superconducting devices have made remarkable progress.

In this paper, we have developed a design environment for a stripe-shaped PMELA process and have designed digital circuits such as a serial-to-parallel converter and a PRBS generator as examples of digital VLSI circuits. The designed circuits and standard cells are fabricated in bulk CMOS process and are verified their operations. The whole circuits are fabricated in PMELA 0.5 mum CMOS technology with 1-poly-Si 1-Metal layers on glass. The measurement results show that digital circuits using PMELA TFTs are successfully integrated on glass by using this design environment.