Implementation of the Exponential Function in a Floating-Point Unit

High-speed datapaths in microprocessors and embedded processors contain complex floating-point (FP) arithmetic units which have a critical role in the processor's performance. Although the FP units' complex structure consists of classic integer arithmetic components, the embedded components encounter serious testability problems due to their limited accessibility from the FP unit ports and testability loss due to FP unit inherent operations, such as rounding and normalization. In this paper, we analyze the testability problems and present scalable test generation for FP units using as a demonstration vehicle the popular, high-speed, two-path architecture of the most complex unit, the FP adder. The key feature of the presented methodology is the identification of testability conditions that guarantee effective test pattern application and fault propagation for each of the components of the FP adder. The identified test conditions can be utilized with respect to any fault model and are independent of the internal structure and the size of the components. Thus, they can be applied to FP adders of various exponent and significant sizes (single, double, and custom precision), as well as to other types of FP units, which also consist of classic integer arithmetic components similarly interconnected

Reversible logic preserves information and provides low power computing. Floating point multiplier is an important part of arithmetic in DSP applications. IEEE754 provide two basic and widely used formats for representing floating point numbers namely Single Precision Floating point (SPFP) and Double Precision Floating Point (DPFP). In this paper, we have proposed designs for Reversible SPFP and DPFP point multiplier which requires optimum design of 24X24 and 53X53 multiplying circuitry with reversible gates respectively. Also we presented sign bit calculation and exponent bit calculation circuits by reversible logic. Reversible Mantissa bits calculation circuitry requires consumes more area as it has large value of quantum cost and garbage outputs as compare to reversible sign bit and exponent bits calculation circuitry. So, we mainly focused our work on to minimize the area consumed by the reversible mantissa bits calculation circuit by minimizing the value of quantum cost and garbage outputs of it. In this paper, we presented two ways for partial products generation with reversible gates. We propose a new design of reversible 12X12 reversible Wallace tree multiplier for single precision and double precision mantissa multiplier circuit. Also 5X5 and 5X12 reversible Wallace tree multiplier for double precision multiplier. Here we use the optimized designs of reversible half adder, Full adder and 4:2 compressors. In the final summation stage, we carefully shifted the product terms and add them. For this stage we have carefully chosen the adders and compressor in such way to get the optimized results in terms of quantum cost and Garbage output. We have also shown the improvement in single precision floating point multiplier in terms of Quantum cost and Garbage output.

Postscaled division is a non-iterative algorithm delivering a quotient of single precision accuracy by the three term product (xy/spl circ/)c and of double precision accuracy by the formula [(xy/spl circ/)c][2-(yy/spl circ/)c]. Here x is the dividend, y/spl circ/ is a low order part complemented form of the divisor y, and c is a table lookup value approximating a 1/(yy/spl circ/) to a precision of over 27 bits. Table lookup latency is hidden by performing the lookup in parallel with the first multiplication (xy/spl circ/), with the second multiplication the postscaling by the lookup function value. Our contribution is the description of two new lookup algorithms for approximating the reciprocal function 1/yy/spl circ/ to high accuracy in fewer cycles than a typical floating point multiply latency. Our indirect bipartite lookup procedure has a latency of two successive lookups followed by a small integer addition. This first algorithm generates a 27 bit approximation of 1/yy/spl circ/ with total table size about 5 Kbytes. Our second lookup algorithm generates a 34 bit approximation with latency determined by 11 and 12 bit table lookups and a 4-1 addition. This second approximation employs some 20 Kbytes of tables to allow for a double extended precision division result in the same number of cycles as a double precision result.

Field Programmable Gate Arrays (FPGAs) are commonly used to accelerate floating-point (FP) applications. Although researchers have extensively studied FPGA FP implementations, existing work has largely focused on standalone operators and frequency-optimized designs. These works are not suitable for FPGA soft processors which are more sensitive to latency, impose a lower frequency ceiling, and require IEEE FP standard compliance. We present an open-source floating-point unit (FPU) for FPGA RISC-V soft processors that is fully IEEE compliant with configurable levels of FP precision. Our design emphasizes runtime performance with 25% lower latency in the most common instructions compared to previous works while maintaining efficient resource utilization. Our FPU also allows users to explore various mantissa widths without having to rewrite or recompile their algorithms. We use this to investigate the scalability of our reduced-precision FPU across numerous microbenchmark functions as well as more complex case studies. Our experiments show that applications like the discrete cosine transformation and the Black-Scholes model can realize a speedup of more than 1.35x in conjunction with a 43% and 35% reduction in lookup table and flip-flop resources while experiencing less than a 0.025% average loss in numerical accuracy with a 16-bit mantissa width.

In digital circuits, particularly space signal applications, the detection/estimation of phase (angle) like milli degree is challenging and involves many complex operations.To estimate milli degree (10-3) or more, floating point operations (like double precision adders, subtractions, multiplications, and divisions) are the significant components and power and area consumption; delays are more in existing works.Existing works mainly concentrate on clock-based synchronous operations, which require more hold, and clock distribution is another major problem due to extra circuitry requirements.The proposed pipelined and clock-efficient distribution system (CEDS) is incorporated in the Floating-Point Unit (FPU) design to address these issues.It includes a double-precision adder, multiplication, division, and subtraction.These FPU and CEDS can be used to detect Milli Degree for GHz frequency in Space applications more accurately.The floating points are essential in phase shift operation used in the space-borne system for effective correction of error checking rather than execution of error analysis in the real-time scenario.Modern digital circuits can hardly improve due to limitations of physical area consumption.The substitution for these limitations, the new digital ternary logic (0, 1, 2), is the solution because of its higher number of digital circuits involved in floating points.The ternary logic is the best solution for the minimization of number bits to optimize memory utilization, and ternary logic has Negative Ternary Inverter (NTI), Ternary Decrement Cycling Inverter (DCI), Standard Ternary Inverter (STI,) and Positive Ternary Inverter (PTI).The proposed design is successfully designed and validated on Zybo Z7-10 (XC7Z010-1CLG400C) FPGA development board.The results show a 45% reduction in power consumption, delay, and area utilization.

This paper introduces a methodology to optimize coarse-grained floating point units (FPUs) in a hybrid field-programmable gate array (FPGA), where the FPU consists of a number of interconnected floating point adders/subtracters (FAs), multipliers (FMs), and wordblocks (WBs). The wordblocks include registers and lookup tables (LUTs) which can implement fixed point operations efficiently. We employ common subgraph extraction to determine the best mix of blocks within an FPU and study the area, speed and utilization tradeoff over a set of floating point benchmark circuits. We then explore the system impact of FPU density and flexibility in terms of area, speed, and routing resources. Finally, we derive an optimized coarse-grained FPU by considering both architectural and system-level issues. This proposed methodology can be used to evaluate a variety of FPU architecture optimizations. The results for the selected FPU architecture optimization show that although high density FPUs are slower, they have the advantages of improved area, area-delay product, and throughput.

In this paper, we have presented a design of hybrid arithmetic logic unit (ALU) in Double precision format (DPF) according to the IEEE-754 standard. In this we have designed an ALU which consists of the two different architectures. First architecture is semi-floating point unit (Semi-FPU) and the second architecture is floating point unit (FPU). Semi-FPU takes a 32-bit integer input and produces an output in 64-bit DPF. And the floating point unit takes the input in 64-bit DPF and produces the output in 64-bit DPF. FPU also provides rounding and exception handling. Both the architectures can perform addition, subtraction, division, and multiplication. ALU is designed with three different adders which is ripple carry adder, carry lookahead adder, and carry save adder. The parameters such as area, power, and delay is compared for each modules (add, mul, div) of ALU with all three different adders. And according to the power-delay product, the best adder among the above three is chosen for each operation. The sub modules are written in Verilog HDL. For simulation we have used Xilinx ISE software and synthesis is done using cadence Encounter RTL compiler using typical libraries of TSMC 45 nm technology.

While ASIPs have allowed designers to create processors with custom instructions to target specific applications, floating point units are still instantiated as fixed general-purpose units, which wastes area if not fully utilized. Therefore, there is a need for custom FPUs for embedded systems. The creation of a custom FPU requires the selection of a subset of the full floating-point instruction set and the implementation of this subset in hardware, such that the runtime of the application is minimized. To minimize area, it is desirable to merge the datapaths for each of the floating-point operations, so that redundant hardware is minimized. Floating-point datapaths are complex and contain components with varying bit-widths, so sharing components of different bit-widths is necessary. However, this introduces the problem of bit-alignment, which involves determining how smaller resources should be aligned within larger resources when merged. This is a problem that has been largely neglected in previous work. Thus, this paper presents a novel algorithm for solving the bit-alignment problem, which neatly integrates into the datapath merging process. By solving this bit-alignment problem, automatic datapath merging can be made available for FPU generation. To explore the trade-offs between area and performance, a rapid design space exploration was performed to determine which FP operations should be implemented in hardware rather than emulated. Our results show that more floating-point hardware does not necessarily equate to lower run-time if the additional hardware increases delay. We found that bit-alignment reduced area by an average of 22.5% in our benchmarks, compared to an average of 14.1% without bit-alignment.

Computation intensive applications such as DSP, image processing, floating point processors and communication technologies today require efficient binary multiplication which usually is the most power and time consuming block. This paper proposes an efficient design for unsigned binary multiplication to reduce delay. A 16×16-bit multiplier has been designed which is based on Vedic Karatsuba algorithm. It is optimized using adaptive and recursive approach combined with square-root-carry-select-adder. The designs have been coded in Verilog, synthesized in Cadence Genus and physically verified with Cadence Innovus in GDSII under ASIC platform.

Design and implementation of Least Mean Square adaptive FIR filter using offset binary coding based Distributed Arithmetic

We propose a modified Goldschimdt reciprocation algorithm for single precision computation, without using a look-up table. It is a variable latency algorithm i.e. the number of iterations depends on the input operands that provide a linear convergence. Multiplying with the dividend results division, our method requires a cycle for each iteration, performing multiply add and Booth recoding in a cycle. Initial approximation is a two's complement of the divisor, which can be performed during partial product summation. The implementation is described in IBM G5 FPU(Floating Point Unit) and MIPS R10000 processor multiplier, evaluated and compared with conventional processors. It offers a good trade-off between performance and area, making it suitable for mobile computing applications such as PDA(Personal Digital Assistant), UPC(Ultra Personal Computer), mobile phone, tablet PC(Personal Computer) etc.

In this paper, multiplication for single precision floating point numbers is analyzed using Vedic multiplier with different techniques. In Vedic multiplier, the full adder is designed using modified 2 × 1 and 4 × 1 multiplexers, 3:2 and 4:2 compressors, and various prefix adders, such as Brent-Kung, Sklansky and Knoules adders for partial products addition. Furthermore, the performance metrics in terms of area and delay comparison is done. From the results, it is concluded that compressor-based Vedic multiplier requires less hardware and prefix adder-based Vedic multiplier is better in terms of delay. The newly introduced changes in Vedic multiplier makes the Vedic multiplier better in performance for the floating point multiplication for single precision numbers using different methods. All modules are coded with Verilog Hardware Description Language and simulated with Xilinx ISE tool.

In recent years, customer demand is for a DSP processor with high and efficient performance. To meet this demand, the hardware is needed which can process the highspeed signal and perform arithmetic floating point operations. Earlier, the majority of algorithms which were implemented onto FPGA were of the fixed point. With the present developments, implementation of floating points on FPGA is becoming a trend because FPGA takes less time for development and less cost compared to ASIC design. The floating point units design needs very high accuracy. In this paper, designing of single precision and double precision floating point arithmetic operations are done and implemented on FPGA for signal processing with the MAC unit using Verilog language. The codes are written in Verilog. The main objective is to compare the area and timing between single and double precision of floating point unit (FPU) and MAC unit. The proposed design is simulated and implemented on Spartan 6 FPGA.

Hardware implementation of the fast Fourier transform (FFT) function consists of multiple consecutive arithmetic operations over complex numbers. Applying floating-point arithmetic to FFT coprocessors leads to a wider dynamic range and allows the coprocessor to collaborate with general purpose processors via the standard floating-point arithmetic. This offloads compute-intensive tasks from the primary processor and overcomes floating-point concerns such as scaling and overflow/underflow detection. The downside, however, is that floating-point units are slower than the fixed-point counterparts. One of the popular ways to improve the speed of floating-point FFT units is to merge the arithmetic operations inside the butterfly units of a FFT architecture. This leads to a butterfly architecture based on multi-operand adders. Butterfly units are designed, in two of the most recent works, using three-operand and four-operand adders. However, the work reported here by the present authors goes further and a butterfly architecture based on a five-operand adder is proposed. Simulation results demonstrate that the proposed butterfly architecture is 50% smaller than the fastest previous work with about 17% latency overhead. Compared with the smallest previous work, the proposed design is 47% smaller and 8% faster.

This brief introduces a low-cost hardware design for approximate squaring functions which preserve maximum information content of the signals in template-matching applications. Analysis of signal statistics for two example applications, i.e., motion estimation and disparity estimation, is presented. This information is then specifically incorporated in the hardware design process to develop approximate squarers which outperform existing designs in hardware resource savings and performance while processing real-world data. Specifically, the proposed architectures make distinction between low- and high-entropy portions of the input data to intelligently trade off bit precision with hardware complexity. Mathematical and experimental results show mean-relative-error figures to be as low as 1.2% and the performance to be as good as conventional full-precision processing scenarios. Implementation results for current-generation six-input look up table (LUT) and four-input LUT FPGAs have been discussed in relation to the proposed design flow.