Rapid application specific floating-point unit generation with bit-alignment

During conceptual design, multidisciplinary optimization is often performed using computationally intensive direct methods. Prior work has shown that rapid design studies can be performed using fast indirect methods, but several optimization techniques including discrete dynamic programming, nonlinear inversion, and pseudospectral methods are required to construct a suitable initial guess within the design space. In this investigation, a simplied methodology is developed to eliminate these optimization techniques, enabling rapid design space exploration using continuation of indirect methods alone. This is made possible by initially converging to a simple solution that is outside of the design space of interest, and solutions within the design space of interest are quickly accessed through continuation from this initial solution. As an initial step to automate this continuation process, state transition tensors are used to predict optimal solutions throughout the design space. A methodology is developed to provide accurate predictions of trajectories with varying ight times, and the error of these predictions is controlled to regulate the continuation process. This approach provides exibility to adapt to future computational capabilities and serves as an initial step to bridge the gap between conceptual trajectory design and onboard trajectory planning.

Hardware implementation of the fast Fourier transform (FFT) function consists of multiple consecutive arithmetic operations over complex numbers. Applying floating-point arithmetic to FFT coprocessors leads to a wider dynamic range and allows the coprocessor to collaborate with general purpose processors via the standard floating-point arithmetic. This offloads compute-intensive tasks from the primary processor and overcomes floating-point concerns such as scaling and overflow/underflow detection. The downside, however, is that floating-point units are slower than the fixed-point counterparts. One of the popular ways to improve the speed of floating-point FFT units is to merge the arithmetic operations inside the butterfly units of a FFT architecture. This leads to a butterfly architecture based on multi-operand adders. Butterfly units are designed, in two of the most recent works, using three-operand and four-operand adders. However, the work reported here by the present authors goes further and a butterfly architecture based on a five-operand adder is proposed. Simulation results demonstrate that the proposed butterfly architecture is 50% smaller than the fastest previous work with about 17% latency overhead. Compared with the smallest previous work, the proposed design is 47% smaller and 8% faster.

Design space exploration is an important part of design in engineering fields. Recent research employs surrogate models to emulate finite element analyses across a design space, allowing rapid design space exploration. With interactive speeds, there exists a need for tools that help designers compare designs to one another. This difference model is comprised of a three-dimensional rendering of the geometry with the location and magnitude of differences between the two designs displayed as colors on the model surface. This visualization is combined with juxtaposed views of the objects being compared. A user experiment was conducted with 28 volunteers to demonstrate whether or not including the difference model in the visualization can improve speed and accuracy for various comparative design tasks. It was found that, for certain comparison tasks, there is indeed statistical evidence that using the difference model alongside the two juxtaposed views improved speed and accuracy when making design judgments between two different designs.

The increasing complexity of embedded systems requires modeling at higher levels of abstraction. Transaction level modeling (TLM) has been proposed to abstract communication for high-speed system simulation and rapid design space exploration. Although being widely accepted for its high performance and efficiency, TLM often exhibits a significant loss in model accuracy. In this article, we systematically analyze and quantify the speed/accuracy trade-off in TLM. To this end, we provide a classification of TLM abstraction levels based on model granularity and define appropriate metrics and test setups to quantitatively measure and compare the performance and accuracy of such models. Addressing several classes of embedded communication protocols, we apply our analysis to three common bus architectures, the industry-standard AMBA advanced high-performance bus (AHB) as an on-chip parallel bus, the controller area network (CAN) as an off-chip serial bus, and the Motorola ColdFire Master Bus as an example for a custom embedded processor bus. Based on the analysis of these individual busses, we then generalize our results for a broader conclusion. The general TLM trade-off offers gains of up to four orders of magnitude in simulation speed, generally however, at the price of low accuracy. We conclude further that model granularity is the key to efficient TLM abstraction, and we identify conditions for accuracy of abstract models. As a result, this article provides general guidelines that allow the system designer to navigate the TLM trade-off effectively and choose the most suitable model for the given application with fast and accurate results.

In this work we present an implementation of the exponential function in double precision, in a unit that supports IEEE floating-point arithmetic. As existing proposals, the implementation is based on the use of a floating-point multiplier and additional hardware. We decompose the computation into three subexponentials. The first and third subexponentials are computed in a conventional way (table look-up and polynomial approximation). The second subexponential is computed based on a transformation of the slow radix-2 digit-recurrence algorithm into a fast computation by using the multiplier and additional hardware. We present a design process that permits the selection of the most convenient trade-off between hardware complexity and latency. We discuss the algorithm, the implementation, and perform a rough comparison with three proposed designs. Our estimations indicate that the implementation proposed in this work presents better trade-off between hardware complexity and latency than the compared designs.

The ever-growing design complexity of modern embedded systems and the need for lower energy consumption have lead to design techniques which target to bridge the gap between the designer's productivity and the design complexity. In particular, Virtual Prototyping enables the system modeling and simulation in multiple abstraction levels, while the automated Design Space Exploration (DSE) targets to find optimized design solutions in a reasonable time. However, there is the need for more efficient techniques for prototyping and co-simulation, as the rapid simulation has become a stringent requirement. In addition, as emerging heterogeneous architectures expose even higher design complexity, typical DSE techniques may not achieve high-quality design solutions. Towards this direction, the proposed design flow introduces (a) a set of prototyping techniques which target to faster but accurate simulation, also supporting the system co-simulation with other environments, and (b) a number of DSE methodologies for high-complexity computation and communication architectures.

Advances in robotics, artificial intelligence, and machine learning are ushering in a new age of automation, as machines match or outperform human performance. Machine intelligence can enable businesses to improve performance by reducing errors, improving sensitivity, quality and speed, and in some cases achieving outcomes that go beyond current resource capabilities. Relevant applications include new product architecture design, rapid material characterization, and life-cycle management tied with a digital strategy that will enable efficient development of products from cradle to grave. In addition, there are also challenges to overcome that must be addressed through a major, sustained research effort that is based solidly on both inferential and computational principles applied to design tailoring of functionally optimized structures. Current applications of structural materials in the aerospace industry demand the highest quality control of material microstructure, especially for advanced rotational turbomachinery in aircraft engines in order to have the best tailored material property. In this paper, deep convolutional neural networks were developed to accurately predict processing-structure-property relations from materials microstructures images, surpassing current best practices and modeling efforts. The models automatically learn critical features, without the need for manual specification and/or subjective and expensive image analysis. Further, in combination with generative deep learning models, a framework is proposed to enable rapid material design space exploration and property identification and optimization. The implementation must take account of real-time decision cycles and the trade-offs between speed and accuracy.

The increasing complexity of embedded systems imposes system designers to use higher levels of abstraction than RTL in order to model, validate and analyze a system performances. It permits to prevent costly redesign efforts at RTL, which can adversely affect time-to-market. For this purpose transaction level modeling (TLM) approach is used. It allows the designers to rapidly verify and develop their designs at earlier design stages. In this paper we define the methodology we used to construct the STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-On-Chip) TLM simulation environment. This platform aims to provide a rapid and accurate design space exploration at higher levels of abstractions for multiprocessor system on chip architectures. The platform reference design contains several OpenRISC 1200 Instruction Set Simulators (ISSs) wrapped under SystemC, and some basic peripherals within the SystemC simulation framework. In order to assist the system designer to find the best MPSoC solution depending on the application, we used SystemC language for modeling and simulating the design. The platform includes models for OpenRISC ISSs, bus model based on wishbone protocol and memory models. The simulation is based on different high level of abstractions.

The increasing number and variety of spacecraft that are expected to operate within cislunar space and other multi-body gravitational environments throughout the solar system necessitates the continued development of strategies for rapid trajectory design and design space exploration. In the field of robotics, similar needs have been addressed using motion primitives that capture the fundamental building blocks of motion and are used to rapidly construct complex paths. Inspired by this concept, this paper leverages motion primitives to construct a framework for rapid and informed spacecraft trajectory design in a multi-body gravitational system. First, motion primitives of fundamental solutions, e.g., selected periodic orbits and their stable and unstable manifolds, are generated via clustering to form a discrete summary of segments of the phase space. Graphs of motion primitives are then constructed and searched to produce primitive sequences that form candidate initial guesses for transfers of distinct geometries. Continuous transfers are computed from each initial guess using multi-objective constrained optimization and collocation. This approach is demonstrated by constructing an array of geometrically distinct transfers between libration point orbits in the Earth-Moon circular restricted three-body problem with impulsive maneuvers.

Automatic design space exploration (DSE) tools have been employed over years to evaluate high-performance computer architectures and software designs via on simulation tools. As today's smartphones and consumer electronic devices have become so complex, DSE tools are needed to speed up the design process and produce better designs for the targeted applications. However, traditional simulation tools are too slow to report good system designs in a timely fashion. Thus, in this paper, we propose a framework, called Android Design Space Exploration Tool (ADSET), to facilitate DSE for modern consumer electronic devices. To shorten the exploration time, we adopt a fast full-system modeling technique in our previous work and further develop a parallel DSE method to concurrently evaluate the multiple design points. In our case study, we show that ADSET is capable of modeling Android smartphones in the market and rapidly finds good designs in a large design space.

BackgroundPrincipal component analysis (PCA) has been widely employed for automatic neuronal spike sorting. Calculating principal components (PCs) is computationally expensive, and requires complex numerical operations and large memory resources. Substantial hardware resources are therefore needed for hardware implementations of PCA. General Hebbian algorithm (GHA) has been proposed for calculating PCs of neuronal spikes in our previous work, which eliminates the needs of computationally expensive covariance analysis and eigenvalue decomposition in conventional PCA algorithms. However, large memory resources are still inherently required for storing a large volume of aligned spikes for training PCs. The large size memory will consume large hardware resources and contribute significant power dissipation, which make GHA difficult to be implemented in portable or implantable multi-channel recording micro-systems.MethodIn this paper, we present a new algorithm for PCA-based spike sorting based on GHA, namely stream-based Hebbian eigenfilter, which eliminates the inherent memory requirements of GHA while keeping the accuracy of spike sorting by utilizing the pseudo-stationarity of neuronal spikes. Because of the reduction of large hardware storage requirements, the proposed algorithm can lead to ultra-low hardware resources and power consumption of hardware implementations, which is critical for the future multi-channel micro-systems. Both clinical and synthetic neural recording data sets were employed for evaluating the accuracy of the stream-based Hebbian eigenfilter. The performance of spike sorting using stream-based eigenfilter and the computational complexity of the eigenfilter were rigorously evaluated and compared with conventional PCA algorithms. Field programmable logic arrays (FPGAs) were employed to implement the proposed algorithm, evaluate the hardware implementations and demonstrate the reduction in both power consumption and hardware memories achieved by the streaming computingResults and discussionResults demonstrate that the stream-based eigenfilter can achieve the same accuracy and is 10 times more computationally efficient when compared with conventional PCA algorithms. Hardware evaluations show that 90.3% logic resources, 95.1% power consumption and 86.8% computing latency can be reduced by the stream-based eigenfilter when compared with PCA hardware. By utilizing the streaming method, 92% memory resources and 67% power consumption can be saved when compared with the direct implementation of GHA.ConclusionStream-based Hebbian eigenfilter presents a novel approach to enable real-time spike sorting with reduced computational complexity and hardware costs. This new design can be further utilized for multi-channel neuro-physiological experiments or chronic implants.

Conventionally, sink node is considered to have large hardware and energy resources; however, many times sink node is working in same conditions as source nodes, especially when deployed for monitoring of the snow environment. In this paper, an effort has been made to practically realize a sink node which is energy efficient and cost effective for monitoring applications. To save energy, the Main Power Module is designed to provide controlled powers to sensors and sub-modules. The paper discusses design aspects of the sink node and its long-term field evaluation with environmental sensors, especially the Snow Depth Sensor of MaxBotix. Field performance of Snow Depth Sensor has been enhanced by Euclidean Minimum Distance filter which improved the correlation of data to 0.997. The proposed design helps to achieve energy consumption of 42.72mWh which is significantly lower than the previous work. The reliable working of the sink node in the long-term field evaluation indicates that snow environment can be monitored at less expense of energy by employing proposed sensors and the specially designed sink node.

This paper proposes a new approach to trajectory pattern mining, which attempts to discover frequent movement patterns from the trajectories of moving objects. For dealing with a large volume of trajectory data, traditional approaches quantize them by a grid with a fixed resolution. However, an appropriate resolution often varies across different areas of trajectories. Simply increasing the resolution cannot capture broad patterns and consumes unnecessarily large computational resources. To solve the problem, the authors propose a hierarchical grid-based approach with quadtree search. The approach initially searches for frequent patterns with a coarse grid and drills down into a finer grid level to discover more minute patterns. The algorithm is naturally parallelized and implemented in the MapReduce programming model to accelerate the computation. The authors’ evaluative experiments on real-word data show the effectiveness of the authors’ approach in mining complex patterns with lower computational cost than the previous work.

This paper describes the performance advantages of a two and four byte variable length instruction set, Thumb2. over a four byte fixed length instruction set, ARM. Both instruction sets are found in ARMv7-A ISA compatible processors, such as the ARM Cortex-A8 and Cortex-A9. The code size reduction when using a variable length instruction set is well understood and can be significant. The focus of this paper is the performance advantage of increased code density. With Thumb2 more instructions are stored in the I-cache, increasing I-cache hit rates, and in turn increasing the performance of the processor. To demonstrate the performance advantage of Thumb2, a Mozilla based web browser built for Thumb2 and ARM on Linux is run in a full system emulator and in a full system instruction set simulator with a cache model. Switching from the ARM four byte fixed length instruction set to the Thumb2 two and four byte variable length instruction set results in a 1.07x improvement in performance and 33% improvement in code density.

The 34010 Graphics System Processor is a 32-bit graphics microprocessor capable of executing high-level languages. It combines a full general-purpose instruction set with a powerful set of graphics instructions that includes arithmetic as well as Boolean pixbits (pixel block transfers). Because it is completely programmable, the 34010 can be used in many different graphics and nongraphics applications. it was designed to support a wide range of display resolutions and pixel sizes, as well as applications such as page (laser) printers, ink jet printers, data compression, and facsimile transmission. The 34010 includes such system features as an on-board instruction cache, full interrupt capability, wait and hold functions, and display timing control, as well as test and emulation support. Unique among today's microprocessors, the 34010 addresses all memory down to the bit level with variably sized fields rather than the common byte or word addressing. For example, the 34010 can push a 5-bit quantity onto a stack. This field-processing capability is an integral part of the basic architecture.