TLM Platform Based on SystemC for STARSoC Design Space Exploration

The increasing complexity of embedded systems requires modeling at higher levels of abstraction. Transaction level modeling (TLM) has been proposed to abstract communication for high-speed system simulation and rapid design space exploration. Although being widely accepted for its high performance and efficiency, TLM often exhibits a significant loss in model accuracy. In this article, we systematically analyze and quantify the speed/accuracy trade-off in TLM. To this end, we provide a classification of TLM abstraction levels based on model granularity and define appropriate metrics and test setups to quantitatively measure and compare the performance and accuracy of such models. Addressing several classes of embedded communication protocols, we apply our analysis to three common bus architectures, the industry-standard AMBA advanced high-performance bus (AHB) as an on-chip parallel bus, the controller area network (CAN) as an off-chip serial bus, and the Motorola ColdFire Master Bus as an example for a custom embedded processor bus. Based on the analysis of these individual busses, we then generalize our results for a broader conclusion. The general TLM trade-off offers gains of up to four orders of magnitude in simulation speed, generally however, at the price of low accuracy. We conclude further that model granularity is the key to efficient TLM abstraction, and we identify conditions for accuracy of abstract models. As a result, this article provides general guidelines that allow the system designer to navigate the TLM trade-off effectively and choose the most suitable model for the given application with fast and accurate results.

Transaction level modeling (TLM) improves the simulation performance by raising the abstraction level. In the TLM 2.0 standard based on OSCI SystemC, a single transaction can transfer a large data block. Due to such high abstraction, a great amount of information becomes invisible and thus timing accuracy can be degraded heavily. We present a methodology to accurately time such block transactions and achieve high simulation performance at the same time. First, before abstraction, a profiling process is performed on an instruction set simulator (ISS). Driver functions that implement the transfer of the data blocks are simulated. Several techniques are employed to trace the exact start and end of the driver functions as well as HW usages. Thus, a profile library of those driver functions can be constructed. Then, the application programs are host-compiled and use a single transaction to transfer a data block. A strategy is presented that efficiently estimates the timing of block transactions based on the profile library. It is the first method that takes into account caching effects that influence the timing of block transactions. Moreover, it ensures overall timing accuracy when integrated in other SW timing tools for full system simulation. Experimental results show that the block transactions are accurately timed, with average error less than 1%. At the same time, the simulation gain can be up to three orders of magnitude.

In recent years, transaction level modeling (TLM) has enabled designers to simulate complex embedded systems and SoCs, orders of magnitude faster than simulation at the RTL. The increasing complexity of the systems on one hand, and availability of low cost parallel processing resources on the other hand have motivated the development of parallel simulation environments for TLMs. The existing simulation environments used for parallel simulation of TLMs are intended for general discrete event models and do not take advantage of the specific properties of TLMs. The fine-grain synchronization and communication between simulators in these environments can become a major impediment to the efficiency of the simulation environment. In this work, we exploit the properties of temporally decoupled TLMs to increase the efficiency of parallel simulation. Our approach does not require a special simulation kernel. We have implemented a parallel TLM simulation framework based on the publicly available OSCI SystemC simulator. The framework is based on the communication interfaces proposed in the recent OSCI TLM 2 standard. Our experimental results show the reduced synchronization overhead and improved simulation performance.

During conceptual design, multidisciplinary optimization is often performed using computationally intensive direct methods. Prior work has shown that rapid design studies can be performed using fast indirect methods, but several optimization techniques including discrete dynamic programming, nonlinear inversion, and pseudospectral methods are required to construct a suitable initial guess within the design space. In this investigation, a simplied methodology is developed to eliminate these optimization techniques, enabling rapid design space exploration using continuation of indirect methods alone. This is made possible by initially converging to a simple solution that is outside of the design space of interest, and solutions within the design space of interest are quickly accessed through continuation from this initial solution. As an initial step to automate this continuation process, state transition tensors are used to predict optimal solutions throughout the design space. A methodology is developed to provide accurate predictions of trajectories with varying ight times, and the error of these predictions is controlled to regulate the continuation process. This approach provides exibility to adapt to future computational capabilities and serves as an initial step to bridge the gap between conceptual trajectory design and onboard trajectory planning.

In this paper the authors present some key concepts concerning the specification language (PSL) utilization in a system level verification flow for system on chip (SoC) designs. As transaction level modeling (TLM) is the de-facto reference model for SoC design flow, the authors evaluate PSL adoption in TLM context. How to save time and effort in the verification phase during system development steps and how to overcome global system verification limitations through a compositional approach are discussed. Two PSL-based techniques, properties re-use and properties refinement, are described and compared in terms of refinement effort and simulation speed delay

In this paper, we propose techniques for fast cycle-approximate multi-processor SoC simulation with timed transaction level models and OS models. Cycle-approximate simulation with an abstract model is widely used for fast validation of a multi-processor SoC in early design stages. However, the performance gain of abstract-level simulation is limited by the overhead of synchronizing multiple concurrent processor/module simulators, which is inevitable in timed simulation. To reduce the synchronization overhead, we adopt the synchronization time-point prediction method, which consists of two phases: static code analysis and dynamic scheduling of synchronizations. In the static analysis phase before simulation, it estimates minimum execution time from every point in the code to the nearest synchronization point. Then, during simulation, it pessimistically predicts the synchronization time-points based on the estimates. The proposed approach targets fast cycle-approximate simulation of a system with delay annotated SW code and transaction level models of HW with dynamic behavior. We present, in this paper, techniques to analyze such abstract models of SW and HW and schedule minimal number synchronizations during cycle-approximate simulation of the models. Experiments show that the approach achieves orders of magnitude higher performance in cycle-approximate multi-processor SoC simulation.

Virtual Platforms, SystemC [1] Simulations for SoCs (System on Chip) is one of the prominent technologies' which is widely used today in the industry for early software development despite hardware availability. SystemC facilitates development of Transaction-Level Models (TLMs) [2][3] for SoC components at higher level of abstraction than RTL. This enables lower modeling effort and higher simulation speeds. Memories and Memory Controllers play significant role in the SoC Architecture right from boot-up of the SoC to the regular functionalities. With the growing complexity of SoC Architecture, SoC comprises different kind of memories and Controllers. All though the access timing, electrical levels, technology, access commands are different for each of the memories, when it comes to simulation model features like electrical levels, technology used etc. are of no impact. If the Simulation abstraction is functional accurate type which is generally used for software development use-case, as the software has no idea on cycle information even the accuracy in memory access timings are not of much significance. Features like interface & interface protocols between controller and memories, state machine synchronization, commands and formats for page programming, page reading, block erasing, pipeline accessing, parameter page reading, error control correction etc. are to be implemented functionally accurate. Considering the increasing number of features and complexity of the Flash Memories and Memory Controllers, the effort involved in developing SystemC TLM models for these is significant and many a time repetitive across different memory models and controllers. One of the challenges in this project is to come up with design solutions for implementing Flash Memories and Memory Controllers which would reduce model development efforts and afford reusability, and secondly to improve the memory accessing time of the implemented memories which in turn to improve simulation speeds a buy-in factor for the customers/simulation users.

This paper presents an approach advocating abstract clocks to represent data-intensive applications executed on multiprocessor systems-on-chip (MPSoCs) for facilitating the exploration of large design spaces. By using abstract clocks, the advocated method characterizes applications defined by multiple loop nests, as well as, useful loop transformations that contribute to an efficient application execution. It combines the advantages of optimizations provided by loop transformations and the precision of information on scheduling captured by the abstract clocks. As a result, it favors a rapid, and yet accurate design space exploration (DSE) of data-intensive systems.

Design space exploration is an important part of design in engineering fields. Recent research employs surrogate models to emulate finite element analyses across a design space, allowing rapid design space exploration. With interactive speeds, there exists a need for tools that help designers compare designs to one another. This difference model is comprised of a three-dimensional rendering of the geometry with the location and magnitude of differences between the two designs displayed as colors on the model surface. This visualization is combined with juxtaposed views of the objects being compared. A user experiment was conducted with 28 volunteers to demonstrate whether or not including the difference model in the visualization can improve speed and accuracy for various comparative design tasks. It was found that, for certain comparison tasks, there is indeed statistical evidence that using the difference model alongside the two juxtaposed views improved speed and accuracy when making design judgments between two different designs.

The ever-growing design complexity of modern embedded systems and the need for lower energy consumption have lead to design techniques which target to bridge the gap between the designer's productivity and the design complexity. In particular, Virtual Prototyping enables the system modeling and simulation in multiple abstraction levels, while the automated Design Space Exploration (DSE) targets to find optimized design solutions in a reasonable time. However, there is the need for more efficient techniques for prototyping and co-simulation, as the rapid simulation has become a stringent requirement. In addition, as emerging heterogeneous architectures expose even higher design complexity, typical DSE techniques may not achieve high-quality design solutions. Towards this direction, the proposed design flow introduces (a) a set of prototyping techniques which target to faster but accurate simulation, also supporting the system co-simulation with other environments, and (b) a number of DSE methodologies for high-complexity computation and communication architectures.

Internet-of-Things (IoT) opens a new world of possibilities for both personal and industrial applications. At the heart of an IoT device, the processor is the core component. Hence, as an open and free instruction set architecture RISC-V is gaining huge popularity for IoT. A large ecosystem is available around RISC-V, including various RTL implementations at one end and high-speed instruction set simulators (ISSs) at the other end. These ISSs facilitate functional verification of RTL implementations as well as early SW development to some extent. However, being designed predominantly for speed, they can hardly be extended to support further system-level use cases such as design space exploration, power/timing/performance validation or analysis of complex HW/SW interactions. In this paper, we propose and implement the first RISC-V based Virtual Prototype (VP) with the goal of filling this gap. We provide a RISC-V RV321M core, a PLIC-based interrupt controller and an essential set of peripherals together with SW debug capabilities. The VP is designed as extensible and configurable platform with a generic bus system and implemented in standard-compliant SystemC and TLM-2.0. The latter point is very important, since it allows to leverage cutting-edge SystemC-based modeling techniques needed for the mentioned use cases. Our VP allows a significantly faster simulation compared to RTL, while being more accurate than existing ISSs. Finally, our RISC-V VP is fully open source to help expanding the RISC-V ecosystem and stimulating further research and development.

This article presents a methodology for the design of Networked Embedded Systems (NESs), which extends Transaction Level Modeling (TLM) to perform system/network design-space exploration. As a result, a new design dimension is added to the traditional TLM refinement process to represent network configuration alternatives. Each network configuration can be used to drive both architecture exploration and system validation after each refinement step. A system/network simulation taxonomy is investigated aiming at precisely identifying the role of cosimulation in system/network design-space exploration. Furthermore, a general criterion to map functionalities to system and network models is presented. As a case study, the proposed methodology is applied to the design of a Voice-over-IP client.

The increasing number and variety of spacecraft that are expected to operate within cislunar space and other multi-body gravitational environments throughout the solar system necessitates the continued development of strategies for rapid trajectory design and design space exploration. In the field of robotics, similar needs have been addressed using motion primitives that capture the fundamental building blocks of motion and are used to rapidly construct complex paths. Inspired by this concept, this paper leverages motion primitives to construct a framework for rapid and informed spacecraft trajectory design in a multi-body gravitational system. First, motion primitives of fundamental solutions, e.g., selected periodic orbits and their stable and unstable manifolds, are generated via clustering to form a discrete summary of segments of the phase space. Graphs of motion primitives are then constructed and searched to produce primitive sequences that form candidate initial guesses for transfers of distinct geometries. Continuous transfers are computed from each initial guess using multi-objective constrained optimization and collocation. This approach is demonstrated by constructing an array of geometrically distinct transfers between libration point orbits in the Earth-Moon circular restricted three-body problem with impulsive maneuvers.

When designing heterogeneous MP-SoCs designers have to take into account various objectives such as power, die size, flexibility, performance or programmability. But to be able to evaluate a given system according to these objectives, it is necessary to know how applications will behave on that system. Since time-to-market is one key factor in chip design, it is important to be able to evaluate these systems at a very early design stage. Today this is usually done with simulations in languages such as Simulink or SystemC. We will show how the behavior of such systems can be analyzed without the need for time-consuming implementations of simulation models. This enables fast evaluation and modification of a given system at a very early design stage allowing efficient pruning of the design space.

While ASIPs have allowed designers to create processors with custom instructions to target specific applications, floating point units are still instantiated as fixed general-purpose units, which wastes area if not fully utilized. Therefore, there is a need for custom FPUs for embedded systems. The creation of a custom FPU requires the selection of a subset of the full floating-point instruction set and the implementation of this subset in hardware, such that the runtime of the application is minimized. To minimize area, it is desirable to merge the datapaths for each of the floating-point operations, so that redundant hardware is minimized. Floating-point datapaths are complex and contain components with varying bit-widths, so sharing components of different bit-widths is necessary. However, this introduces the problem of bit-alignment, which involves determining how smaller resources should be aligned within larger resources when merged. This is a problem that has been largely neglected in previous work. Thus, this paper presents a novel algorithm for solving the bit-alignment problem, which neatly integrates into the datapath merging process. By solving this bit-alignment problem, automatic datapath merging can be made available for FPU generation. To explore the trade-offs between area and performance, a rapid design space exploration was performed to determine which FP operations should be implemented in hardware rather than emulated. Our results show that more floating-point hardware does not necessarily equate to lower run-time if the additional hardware increases delay. We found that bit-alignment reduced area by an average of 22.5% in our benchmarks, compared to an average of 14.1% without bit-alignment.