On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling

In this work, a system level design and conception of a System-on-a-Chip (SoC) for the execution of cognitive agents in robotics will be presented. The cognitive model of the Concurrent Autonomous Agent (CAA), which was already successfully applied in several robotics applications, is used as a reference for the development of the hardware architecture. This cognitive model comprises three levels that run concurrently, namely the reactive level (perception-action cycle that executes predefined behaviours), the instinctive level (receives goals from cognitive level and uses a knowledge based system for selecting behaviours in the reactive level) and the cognitive level (planning). For the development of such system level hardware model, the C++ library SystemC with Transaction Level Modelling (TLM) 2.0 will be used. A system model of a module that executes a knowledge based system is presented, followed by a system level description of a processor dedicated to the execution of the Graphplan planning algorithm. The buses interconnecting these modules are modelled by the TLM generic payload. Results from simulated experiments with complex knowledge bases for solving planning problems in different robotics contexts demonstrate the correctness of the proposed architecture. Finally, a discussion on performance gains takes place in the end.

System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems. System designers typically use Bus Cycle Accurate (BCA) models written in high level languages such as C/C++ to explore the communication design space. These models capture all of the bus signals and strictly maintain cycle accuracy, which is useful for reliable performance exploration but results in slow simulation speeds for complex designs, even when they are modeled using high level languages. Recently there have been several efforts to use the Transaction Level Modeling (TLM) paradigm for improving simulation performance in BCA models. However these BCA models capture a lot of details that can be eliminated when exploring communication architectures.In this paper we extend the TLM approach and propose a new and faster transaction-based modeling abstraction level (CCATB) to explore the communication design space. Our abstraction level bridges the gap between the TLM and BCA levels, and yields an average performance speedup of 55 over BCA models. We demonstrate how fast and accurate exploration of tradeoffs is possible for high-performance shared bus architectures such as AMBA 2.0 and AMBA 3.0 (AXI) in industrial strength designs at the proposed abstraction level.

The new trend in designing reconfigurable system-on-chip (SoC) by using embedded FPGAs provides numerous improvements to ASIC designs due to added flexibility and improvements in functionality. Further advantages are introduced if FPGA is provided as a synthesis to core that fits well in the SoC architecture and design flow. This paper proposes and investigates different design of switch-boxes suitable for synthesis in reconfigurable coarse-grain architectures. The various designs are evaluated and compared in terms of power consumption, area, delays and routability.

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.

System on Chip (SoC) designs inherit all the well known verification and validation difficulties associated with complex ASIC designs, besides adding their own set of newer problems. These arise because SoCs are primarily implemented by re-using Intellectual Property (IP) cores. It is well known that verification today constitutes about 70% to 80% of the total design effort, thereby, making it the most expensive component in terms of cost and time, in the entire design flow. It is expected to get even worse for SoC designs. In a complex SoC design flow functional verification is very important; any behavioral or functional bug escaping this phase will not be detected in the subsequent implementation phases and will surface only after the first silicon is integrated into the target system, resulting in costly design and silicon iterations. A number of academic and industrial research laboratories have been carrying out research on functional verification of SoCs based on different approaches. Partial success has been achieved in deploying them. Many of the issues relate to intrinsic limitations of some of the approaches taken; while others have to do with the quality of the design information, by way of, design descriptions, design documentations and design specifications, from which the overall verification objectives are derived. SoCs have brought to focus the need to carry out design and verification concurrently. For the design and verification task to proceed concurrently there is a need to capture formally, design information and implementation details at various levels of abstraction. Another reason for the need to formalize is that, as designs become more complex, functional verification will have to be carried out using the divide and conquer approach.We discuss several approaches based on compositional verification. For these approaches to succeed, specifications of either, the individual modules, or individual IPs, if any are used, have to be stated formally. There exist several commercial offerings addressing the area of SoC functional verification. Most of these use some form of divide and conquer approach related to compositional verification. The basis of success of some of these tools lies in the fact that the specifications of the IP cores are in essence captured in some executable form, be they formal specification languages, or commonly used HDLs suitably modified for the purpose.This tutorial is structured to provide information on the state of the art in the area of functional verification. It will focus on existing methodologies, tools, and practical approaches based on universal simulation, emulation, formal verification, and semi-formal verification that can be employed to overcome the SoC verification problem. We discuss a number of real life verification projects, describing the various techniques used and the effectiveness of these techniques. We conclude the tutorial by presenting issues, which form the current focus for research.

Currently, system-on-chip (SoC) designs are becoming increasingly complex, with more and more components being integrated into a single SoC design. Communication between these components is increasingly dominating critical system paths and frequently becomes the source of performance bottlenecks. It, therefore, becomes imperative for designers to explore the communication space early in the design flow. Traditionally, system designers have used Pin-Accurate Bus Cycle Accurate (PA-BCA) models for early communication space exploration. These models capture all of the bus signals and strictly maintain cycle accuracy, which is useful for reliable performance exploration but results in slow simulation speeds for complex, designs, even when they are modeled using high-level languages. Recently, there have been several efforts to use the Transaction-Level Modeling (TLM) paradigm for improving simulation performance in BCA models. However, these transaction-based BCA (T-BCA) models capture a lot of details that can be eliminated when exploring communication architectures. In this paper, we extend the TLM approach and propose a new transaction-based modeling abstraction level (CCATB) to explore the communication design space. Our abstraction level bridges the gap between the TLM and BCA levels, and yields an average performance speedup of 120% over PA-BCA and 67% over T-BCA models, on average. The CCATB models are not only faster to simulate, but also extremely accurate and take less time to model compared to both T-BCA and PA-BCA models. We describe the mechanisms that produce the speedup in CCATB models and also analyze how the achieved simulation speedup scales with design complexity. To demonstrate the effectiveness of using CCATB for exploration, we present communication space exploration case studies from the broadband communication and multimedia application domains.

Transaction level (TL) models are key to early design exploration, performance estimation and virtual prototyping. Their speed and accuracy enable early and rapid System-on-Chip (SoC) design evaluation and software development. Most devices have only register transfer level (RTL) models that are too complex for SoC simulation. Abstracting these models to TL ones, however, is a challenging task, especially when the RTL description is too obscure or not accessible. This work presents a methodology for automatically creating a TL model of an RTL memory controller component. The device is treated as a black box and a multitude of simulations is used to obtain results, showing its timing behavior. The results are classified into conditional probability distributions, which are reused within a TL model to approximate the RTL timing behavior. The presented method is very fast and highly accurate. The resulting TL model executes approximately 1200 times faster, with a maximum measured average timing offset error of 7.66%.

The increasing complexity of embedded systems imposes system designers to use higher levels of abstraction than RTL in order to model, validate and analyze a system performances. It permits to prevent costly redesign efforts at RTL, which can adversely affect time-to-market. For this purpose transaction level modeling (TLM) approach is used. It allows the designers to rapidly verify and develop their designs at earlier design stages. In this paper we define the methodology we used to construct the STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-On-Chip) TLM simulation environment. This platform aims to provide a rapid and accurate design space exploration at higher levels of abstractions for multiprocessor system on chip architectures. The platform reference design contains several OpenRISC 1200 Instruction Set Simulators (ISSs) wrapped under SystemC, and some basic peripherals within the SystemC simulation framework. In order to assist the system designer to find the best MPSoC solution depending on the application, we used SystemC language for modeling and simulating the design. The platform includes models for OpenRISC ISSs, bus model based on wishbone protocol and memory models. The simulation is based on different high level of abstractions.

Transaction-Level Models (TLM) are used for the early validation of embedded software. A TL model is a virtual prototype of the hardware part of a System-on-a-Chip (SoC). When using SystemC for transaction level modeling, the main parallel entities of the hardware platform (processors, DMAs, bus arbiters, etc.) are modeled by asynchronous processes, which are scheduled at simulation time. The specification of this scheduling mechanism is non-deterministic; the set of all possible schedulings of the parallel activities represents the physical parallelism faithfully. Moreover TL models may contain loose timing annotations (intervals for instance), and the set of all possible values of time in these intervals is also meant to represent the hardware behaviors faithfully. However, any simulation engine is built on a deterministic scheduler, and at runtime will use specific values in the time intervals. This means that only a very small subset of all the possible schedulings and timings are exhibited during simulation. Some bugs may be missed if they are due to some behaviors of the hardware that are represented by other schedulings or timings. For a given finite test scenario, the set of valid schedulings and timings of a model is finite, but far too large to be explored fully. We present a solution to cover the set of schedulings and timings efficiently. Our solution is based on dynamic partial order reduction and constraint solving techniques. It gives a complete scheduling and timing set, which guarantees the detection of all local errors and deadlocks for a fixed test scenario.

Intel® CoFluent™ Studio is a visual model-driven development (MDD) solution for creating executable specifications of complex systems. It can be used at any point of the project lifecycle for modeling and validating any electronic or information systems in any application domain: hardware block, software stack, System-on-Chip (SoC), mixed hardware/software embedded system, networked/distributed system, end-to-end Internet-of-Things (IoT) infrastructure and Big Data networks. Intel CoFluent Studio can predict performance data from the application and use cases model execution on a multicore/multiprocessor platform model. Intel CoFluent Studio is a system modeling and simulation toolset based on Eclipse. Models are captured in graphical diagrams using Intel CoFluent optimized domain-specific language (DSL) or standard UML notations—a combination of SysML and the MARTE profile. ANSI C or C++ is used as action language to capture data types and algorithms. Non-functional system requirements or model calibration data such as execution durations, power, or memory values, are added through model attributes. Models are translated into transaction-level modeling (TLM) SystemC code for execution. The SystemC code is instrumented and generates traces that can be monitored with various analysis tools. Fast host-based simulations allow designers to observe the real-time execution of their application models on multiprocessor/multicore platform models. Performance figures such as latencies, throughputs, buffer levels, resource loads, power consumption, memory footprint, and cost can be extracted.

Recent advances in FPGA technology and the proliferation of High Level Synthesis (HLS) tools makes it possible to implement complex System on Chip (SoC) designs that realize complete applications in a single FPGA device. To be able to exploit the large performance vs. area search space of such modern FPGA-based SoCs, system architects must have the appropriate performance analysis tools to evaluate-preferably at runtime-the computational requirements and the data flow of such a system to determine potential performance bottlenecks when running realistic workloads. In this paper we introduce SoCLog, a framework that automatically enhances the platform architecture with additional hardware components used to generate activity logs when the base SoC architecture executes an application. This real-time information can be analyzed by the system designer to expose performance bottlenecks not only on aggregate, but also at clock cycle granularity thus revealing potential design inefficiencies when there is burst of activity in the system. We evaluate our framework with a number of SoC designs to show that such a logging information can be valuable for the design of a complex SoC in a modern FPGA with minimal area overhead.

System on Chip (SoC) design in the forthcoming billion-transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. The success of this approach depends on the seamless integration of cores like processors, memories, UARTs, etc. Some of the main problems in future SoC designs arise from non scalable global wire delays, failure to achieve global synchronization, errors due to signal integrity issues and difficulties associated with non scalable bus-based functional interconnects. These problems can be addressed by using a network-centric approach to design SoCs, where instead of global wiring, IP blocks are integrated using a switch-based on-chip interconnection network. One of the major concerns with interconnection networks is throughput degradation due to idle physical channels. By introducing the concept of virtual channels in an on-chip interconnection network, the overall throughput of the SoC can be improved. To achieve this throughput improvement, extra silicon area is required but the overall area consumed by the switches can be made to amount to a very small portion of a billion transistor SoC.

In this modern technology era, in System on Chip (SoC) design, performance of processing units in computer is always on demand. By having hardware accelerators in computer system, core processor can offload task to it and this creates parallel execution to improve the processing speed. One of the functional blocks that are crucial in Hardware Accelerator's design is Storage Unit, which is used to keep data that is needed for processing or either the processed data. Under conventional hardware accelerator's design, the storage architecture is shaped to suit a certain processing algorithm and this introduced less flexibility in SoC design. In this paper, a novel design of storage architecture that is able to handle multiple accelerator engines and also modular to typical specification of hardware accelerators has been implemented.

Verification demands for system on chip (SoC) design looms as one of the most significant challenges to designers. With the substantial costs and increasing importance of system verification technologies, determining the best verification strategy is critical to SoC design and business success. The paper focuses on how a designer can apply a model to perform tradeoffs between the different types of emulation, hardware acceleration, and simulation verification tools available. The predictive power of the modeling approach is applied to usage scenarios to determine the most appropriate verification strategy to employ in current or future SoC development efforts.

Design teams find themselves facing decreasing power budgets while simultaneously the products that they design continue to require the integration of increasingly complex levels of functionality. The market place (driven by consumer preferences) and new regulations and guidelines on energy efficiency and environmental impact are the key drivers. This in turn has generated new approaches in all IC and electronic system design domains from the architecture to the physical layout of ICs, to design-for-test, as well as for design verification to insure that the design implementation actually meets the intended requirements and specifications. This chapter covers key aspects of these forces from a technological and market perspective that are driving designers to produce more energy-efficient products. Observations by significant industry leaders from AMD, ARM, IBM, Intel, nVidia and TSMC are cited, and the emerging techniques and technologies used to address these issues now and into the future are explored. Topic areas include: System level: Architectural analysis and transaction-level modeling. How architectural decisions can dramatically reduce the design power and the importance of modeling hardware and software together. IC (Chip) level: The impact of creating on-chip power domains for selectively turning power off and/or multi-voltage operation on: (1) chip verification, (2) multi-corner multi-mode analysis during placement and routing of logic cells and (3) changes to design-for-test, all in order to accommodate for power-gating and multi-voltage control logic, retention registers, isolation cells and level shifters needed to implement these power saving techniques. Process level: The disappearing impact of body-bias techniques on leakage control and why new approaches like High-K Metal Gate (HKMG) technology help but don’t eliminate power issues. Power-efficient design is impacting the way chip designers work today, and this chapter focuses on where the most significant gains can be realized and why power-efficiency requirements will continue to challenge designers into the future. Despite new process technologies, the future will continue to rely on innovative design approaches.