Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCs

The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance, power, and reliability requirements demanded by the next generation of manycore architectures. Recently, emerging on-chip communication technologies, like wireless Networks-on-Chip (WiNoCs), have been proposed as candidate solutions for addressing the scalability limitations of conventional multi-hop NoC architectures. In a WiNoC, a subset of network nodes are equipped with a wireless interface which allows them long-range communication in a single hop. Assessing the performance and power figures of NoC and WiNoC architectures requires the availability of simulation tools that are often limited on modeling specific network configurations. This article presents Noxim, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC, which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures.

The application of the multistage interconnection networks (MINs) in systems‐on‐chip (SoC) and networks‐on‐chip (NoC) is hottest since year 2002. Nevertheless, nobody used them practically for parallel communication. However, to overcome all the previous problems, a new method is proposed that uses MIN to provide intra‐(global) communication among application‐specific NoCs in networks‐in‐package (NiP). For this, four O(n)2 fault‐tolerant parallel algorithms are proposed. It allows different NoCs to communicate in parallel using either fault‐tolerant irregular Penta multistage interconnection network (PNN) or fault‐tolerant regular Hexa multistage interconnection network (HXN). These two are acting as an interconnects‐on‐chip (IoC) in NiP. Both IoC use packet switching and wormhole switching to route packets from source NoC to destination NoC. The results are compared in terms of packet losses and wormhole switching which comes out to be better than packet switching. The comparison of IoC on cost and MTTR concluded that the HXN has the higher cost than the PNN, but MTTR values of the HXN are low in comparison to the PNN. This signifies that the ability to tolerate faults and online repairing of the HXN is higher and faster than the PNN.

In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is the router which dominants the performance of NoC. A baseline router incorporates the FIFO (First In First Out) buffers, the routing computation logic, the arbiter and the crossbar switch fabric. In this paper, we propose different techniques of merging arbitration and switching functionalities accomplished in wormhole NoC router. Proposed microarchitectures for merging these functionalities are Merged Arbitration and Switching (MAS) microarchitecture based on multiplexer reorganization, Pipelined Merged Arbitration and Switching (PMAS) microarchitecture based on Pipelining and Wave-pipelined Merged Arbitration and Switching (WMAS) microarchitecture based on Wave-pipelining. Synthesis results show that the MAS microarchitecture outperforms the Merged ARbiter and multipleXer (MARX) microarchitecture in area and power consumption by 21.8% and 39.5% respectively. Simulation results show that the PMAS and WMAS microarchitectures outperform MARX microarchitecture in throughput by 40% and 60% respectively at a marginal cost of area and power consumption. Therefore, the benefits of using MAS microarchitecture in wormhole NoC router is low area and power consumption and PMAS or WMAS microarchitecture is high throughput.

High-performance supercomputers generally comprise millions of CPUs in which interconnection networks play an important role to achieve high performance. New design paradigms of dynamic on-chip interconnection network involve a) topology b) synthesis, modeling and evaluation c) quality of service, fault tolerance and reliability d) routing procedures. To construct a dynamic highly fault tolerant interconnection networks requires more disjoint paths from each source-destination node pair at each stage and dynamic rerouting capability to use the various available paths effectively. Fast routing and rerouting strategy is needed to provide reliable performance on switch/link failures. This paper proposes two new architecture designs of fault tolerant interconnection networks named as reliable interconnection networks (RIN-1 and RIN-2). The proposed layouts are multipath multi-stage interconnection networks providing four disjoint paths for all the source-destination node pairs with dynamic rerouting capability. The designs can withstand switch failures in all the stages (including input and output stages) and provide more reliability. Reliability analysis of various MIN architectures is evaluated. On comparing the results with some existing MINs it is evident that the proposed designs provides higher reliability values and fault tolerance.

With continued Moore's law scaling, multicore-based architectures are becoming the de facto design paradigm for achieving low-cost and performance/power-efficient processing systems through effective exploitation of available parallelism in software and hardware. A crucial subsystem within multicores is the on-chip interconnection network that orchestrates high-bandwidth, low-latency, and low-power communication of data. Much previous work has focused on improving the design of on-chip networks but without more fully taking into consideration the on-chip communication behavior of application workloads that can be exploited by the network design. A significant portion of this paper analyzes and models on-chip network traffic characteristics of representative application workloads. Leveraged by this, the notion of globally coordinated on-chip networks is proposed in which application communication behavior-captured by traffic profiling-is utilized in the design and configuration of on-chip networks so as to support prevailing traffic flows well, in a globally coordinated manner. This is applied to the design of a hybrid network consisting of a mesh augmented with configurable multidrop (bus-like) spanning channels that serve as express paths for traffic flows benefiting from them, according to the characterized traffic profile. Evaluations reveal that network latency and energy consumption for a 64-core system running OpenMP benchmarks can be improved on average by 15 and 27 percent, respectively, with globally coordinated on-chip networks.

In Network-on-chip design two of the most important performance indices are the average delay of packets and power dissipation. The first depends on the level of congestion of the communication system, the second is strongly influenced by the power dissipated by the links of a network-on-chip (NoC) which accounts for a significant fraction of the overall power dissipated by the on-chip communication fabric. Such fraction becomes more and more relevant as technology shrinks. The selection policy of the output port in the NOC router with adaptive routing function affects both the performance and power dissipation. In fact, generally a NOC with a lower average delay has a lower power dissipation on the links for transmission. The selection policies proposed in the literature have the object or the minimization of the average delay or in some cases the reduction of power dissipation. In this paper we propose a selection policy aimed at minimizing both the average delay and power consumption of the communication system of NoC based architectures. The proposed policy uses a cost function obtained using a Fuzzy Rule Base System (FRBS) with two inputs an one output. Inputs are the level of use of the buffers of the downstream routers, and the link power dissipation of the selected output. The output of FRBS is the cost function. The experimental results, obtained using a cycle accurate NoC simulator for different traffic scenarios, shows that the proposed selection policy outperforms other selection approaches both in terms of average delay and in terms on power dissipation and energy consumption.

Network on Chips(NoC) emerged as the reliable communication framework in CMPs and SoCs which enables in increase the number and complexity of cores. Many 2-D NoC architectures have been proposed for efficient on-chip communication. Cycle accurate simulators model the functionality and behavior of NoCs by considering micro-architectural parameters of the underlined components to estimate performance metric. Using 3D IC technology in NoC can lead to improved communication latency and power compared to their 2D counterpart with use of through-silicon via (TSVs) as vertical interconnect. In this paper, we explore the design space of 3D variants of the Mesh and Butterfly Fat Tree(BFT) NoCs using floorplan driven wire and TSV lengths. Analysed the performance of 2D and 3D variants of the Mesh and BFT topologies by injecting uniform traffic pattern. Results of our experiments show that, average network latency of a 4-layer 3D Mesh shows better on-chip communication performance compare to other 3D variants. In 4-layer 3D Mesh, on-chip communication performance is improved up to 2.2× compare to 2D Mesh and 4.5× compare to 4-layer 3D BFT.

The density of integration in a single chip has progressed by use of the deep submicron of VLSI design rule. Systems on a chip (for short, SoCs), i.e., several functional cores being integrated in a single chip, have become the mainstream technology. On the other hand, A Network on a Chip (NoC), i.e., a communication-centric platform, offers an on-chip interconnection network. The NoC is one of the on-chip communication systems. The NoC is used in place of conventional shared bus systems. There are many NoC topologies for connecting cores to each other, such as Mesh, Ring, Spider on, and so on. To evaluate the NoC topologies, a simulation based approach was used for the modeling and analysis of the topologies. However, some properties of the topologies could affect the performance of the NoC systems. This paper describes about the performances of the topologies about the communication aspects by the simulation based approach.

Network on Chips (NoC) have emerged as a reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. The use of 3D IC technology in NoC promises to improve communication latency and power. Most of the 3D ICs use Through-silicon via (TSVs) as vertical interconnect. In this paper, we explore the design space of 2-layer 3D Butterfly Fat Tree (BFT) variants. Floorplan driven wire and TSV lengths are used to obtained power and performance optimal 3D NoC architectures. We analysed the performance of the output flow control using random and round robin output based deflection routing for 3D BFT variants. TSV based power and delay models were extended to a cycle accurate simulator to estimate accurate power and performance of 3D NoC architecture. We propose a new OP3DBFT (Optimal Power and Performance 3DBFT) architecture with round-robin deflection routing (RROD) as power and performance optimal 2-layer 3D NoC architecture. OP3DBFT has symmetric link lengths and 75% of TSVs count reduced compared to the regular 2-layer 3D BFT topology. Results of our experiments show that the performance improved up to 1.39\(\times \) and 1.3\(\times \) in OP3DBFT with fewer TSV counts compared to the regular 2-layer 3D BFT for uniform and transpose traffic respectively. The OP3DBFT NoC architecture EDP (Energy delay product) was lower by 40% for uniform traffic and 48% for transpose traffic.

NoC (Network on Chip) is an emerging paradigm for design of VLSI/ULSI circuits to overcome communication bottleneck of traditional bus based systems. NoC communication framework consists of regularly placed routers, which are connected to processing cores. NoC performance is determined by latency and throughput for communication requirements. NoC communication traffic modelling plays an important role in design of NoC simulators and/or prototypes. This paper presents a framework for modelling source traffic for multipoint communication from one source to different destinations as is required for multicasting. Such a traffic model captures real-world scenarios such as multicasting, execution of concurrent multiple tasks on a single core (each task requiring communication with different destinations). The model proposes how concurrent traffic streams from a single core to different destinations can be mathematically characterized as a single stream at source end. The model is derived from statistical behaviour of probabilistically demultiplexing of a single traffic stream. In its nascent stage, the method is proposed for a scenario of one source concurrently communicating with two destinations as shall be required for mapping two concurrent tasks to same core or simultaneous broadcast to two destinations.

The authors propose an enhancement to the Tagle-Sharma network, a high performance self routing fault tolerant switch fabric which employs an enhanced scheme of the banyan network. The enhancement incorporates a shared-buffer in each switching element (SE) of the network to handle evolving traffic in converged networks. Two buffering management schemes are also proposed: the first-in-first-out (FIFO) configuration which employs backpressure control flow mechanism and follows the FIFO policy in handling the buffer; and the look-ahead configuration which still follows all the features of the FIFO scheme but uses the buffer only when needed. Simulation experiments under uniform random traffic are performed to measure the throughput, and average transmission delay of the switching networks. The Tagle-Sharma network is compared with the parallel banyan and the Benes networks. The results suggest that providing small buffers in the SEs can significantly improve the throughput performance of buffered switch architectures. Tagle-Sharma switching network performs better than the other Multistage Interconnection Network (MIN) designs. Furthermore, the look-ahead configuration performs better than the FIFO scheme.

The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication through packet based networks. In NOC topology, routing algorithm and switching are main terminology. The routing algorithm is one of the key factors in NoC architecture. The routing algorithm which defines as the path taken by a packet between the source and the destination. The paper proposes a novel algorithm for a Network-on-Chip, which is based on packet switching. Using square mesh techniques used for 16 nodes based NoC design and simulation. The node is equal to row and column. Paper discusses internal architecture of NoC using addressable memory and simulate on XILINX 14.1 ISE MODELSIM. Keywords : Network-on-Chip, Static routing, Parallelism Cite this Article Anurag Shrivastava, Sudhir Kumar Sharma. A reliable routing architecture and algorithm for network-on-chip, Journal of Electronic Design and Technology . 2015; 6(3): 40–48p.

Network delay is a major design parameter for Networks-on-Chip (NoC)-based applications. Improving NoC delay could be achieved at different design phases. At the system level, we study in this paper the impact of the network topology on NoC system delay using graph-theoretic concepts. A topology-based model is developed to calculate the average NoC delay, which is caused by links and routers. The proposed model could be used to select the optimal topology that achieves the minimum network delay for a given NoC application. A case study is presented to show how this model could be used to improve the delay of a given NoC application at early design phases.

An interconnection network for a high-performance parallel computer for database, Lisp and Prolog applications is currently being developed. To meet the requirements derived from applications a multistage interconnection network is chosen. The selection of the switching elements and their optimization was done by simulation with randomly distributed load patterns as well as with traces from applications. The proposed network is composed of 8 × 8 crossbar switches with four independent packet buffers per input port. Each switch will be contained in a single VLSI-chip. The network will operate with a bandwidth of 20 Mbytes/sec on each communication channel.Key Wordsbuffering schemecrossbar switchdelta networknetwork simulationparallel computervirtual cut-through

The editors view an ongoing development effort of NoC architectures toward an increased dynamism and flexibility as headed to a new milestone for NoC technology. The book does not intend to miss the opportunity to join this exciting ride, and presents in a coherent and systematic fashion both stabilized and less stabilized topics, with the level of detail enabled by their state-of-the-art, thus hopefully helping understand what is going on in the NoC community and serving as stepping stone into future chip multiprocessor architectures.