Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability

The fabricated circuitries are getting massive and denser with every passing year due to which a normal automatic test pattern generation technique to detect only the single stuck-at faults will overlook the multiple stuck-at faults. But generating test patterns that can detect all possible multiple stuck-at fault is practically not possible. Hence, this paper proposes a method, where multiple faults can be detected by using test vectors for detecting single stuck-at faults. Here, the patterns for detecting single faults are generated and their ability to detect multiple stuck-at faults is also analyzed. From the experimental results it was observed that, the generated vectors for single faults cover maximum number of the multiple faults and then new test vectors are generated for the undetermined faults. The generated vectors are optimized for the compact test patterns in order to reduce the test power.

Null Convention Logic (NCL) is a robust asynchronous technique that poses new challenges to test and testability strategies due to the lack of a clock signal and the state-holding behavior of the NCL gates. The lack of deterministic timing in NCL complicates the management of test timing, and stuck-at faults on gate internal feedback (GIF) of the NCL gates exhibit a totally different effect compared to that of stuck-at faults on the gate inputs. Stuck-at faults on gate internal feedback of NCL gates do not always cause an incorrect output and therefore are considered hard-to-detect or undetectable by automatic test pattern generation (ATPG) algorithms. Such faults could leave the primary outputs of the circuit completely unaffected or sometimes they only affect the circuit by early detection of completeness. This work first proposes a clock-less self-timed ATPG, with no added design for test (DFT), that detects all of the faults on the gate inputs and a share of those on the GIF of gates. Then, this work investigates the effectiveness of <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IDDQ</sub> (quiescent current) test for detecting stuck-at faults on GIF of NCL gates. Hspice is used for implementing static and semi-static transistor-level NCL gates in (45 nm, 1.1 V) technology, for which the supply current is measured and compared for fault-free and faulty circuits. The experimental results show that the faulty current is orders of magnitude higher than the fault-free leakage current. This considerable difference shows that I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDQ</sub> testing might be an efficient and low-cost candidate for detecting stuck-at faults on GIF of NCL gates. The proposed I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDQ</sub> test method along with the self-timed ATPG has resulted in average 98.16 and 98.04 percent fault coverage for static and semi-static implementations of several NCL circuits, respectively. To the extent of our knowledge, this is the first work that has addressed clockless, self-timed ATPG for NCL with no area overhead, and also the first work conducted on I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDQ</sub> test for NCL.

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure.

In this paper a polynomial time algorithm for the minimization of Fixed Polarity Reed-Muller Expressions (FPRMs) for totally symmetric functions based on Ordered Functional Decision Diagrams (OFDDs) is presented. A generalization to partially symmetric functions is investigated. The algorithm has been implemented as the program Sympathy. Experimental results in comparison to previously published methods are given to show the efficiency of the approach. >

This paper continues the series based on the use of matrices in the design of switching networks. To avoid redundancy within the series, all previous papers on matrix logic are considered as prerequisite, in particular, references 1 and 2. This paper establishes a general classification scheme for logical functions, as follows: 1. General symmetric functions, which are the sum of ordinary symmetric functions. 2. Trivial and redundant functions. 3. Universal functions, which are capable of performing any logical functions by appropriate iterations.

The presence of an undetectable fault <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> may modify the response of a detectable fault <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> to a test set used for fault diagnosis. This may impact the accuracy of fault diagnosis based on the responses of single faults. Many state-of-the-art diagnosis processes are based on the responses of single stuck-at faults even though their goal is to diagnose defects (including multiple defects) that are different from stuck-at faults. Therefore, we study the effects of undetectable single stuck- at faults on the accuracy of fault diagnosis based on the responses of single stuck-at faults. For this purpose, we consider the cases where the response of a double stuck-at fault <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> & <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> , which consists of an undetectable fault <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> and a detectable fault <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> , is different from the response of the single fault <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> . We show that there are significant, yet manageable, numbers of such faults in benchmark circuits under test sets used for fault diagnosis. In all these cases, a fault diagnosis process based on single stuck-at faults may not identify the locations of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> as candidate defect sites if a defect affects the sites of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> . We conclude that it is important to consider <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> & <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> during fault diagnosis in order not to preclude the sites of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> as candidate defect sites.

All the totally self checking (TSC) circuits known so far [3]-[8] restrict their fault sets to either single or multiple but unidirectional stuck-at faults. Meyer and Sundstrom [20] have considered on line diagnosis of unrestricted faults but the class of circuits proposed by them does not fall under the category of TSC circuits. This paper proposes a new type of circuit model which is TSC for a fault set, consisting of all possible, i.e., unrestricted stuck-at faults on all the gate input and output signal lines. The model uses redundancy in both space and time domains and realizes combinatorial functions. Some important properties of the model are brought out by a set of lemmas and theorems. The viability of the model is demonstrated by a circuit example which uses CMOS technology.

Due to the continuous shrinking of semiconductor technology, there are more and more subtle errors or faults widely distributed in manufactured chips, and traditional "single" stuck-at fault model may become inappropriate. It is definitely better if all combinations of multiple faults can be completely tested. In this paper, we present ATPG (Automatic Test Pattern Generation) techniques targeting all multiple stuck-at faults, i.e. all combinations of stuck-at faults. That is, given "n" possibly faulty locations in a circuit, the target set of faults consists of 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1 fault combinations, as each possibly faulty location is under stuck-at 1, stuck-at 0, or normal/non-faulty. Traditional ATPG flows use fault simulators to eliminate all detectable faults by the current set of test vectors. The problem, however, fault simulators represent fault lists explicitly in the sense that all possible faults are enumerated in the fault lists. This prevents us from dealing with ultra large fault lists, such as 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1 faults. We need "implicit" representation of faults in order to deal with such huge numbers of faults or fault combinations. We present SAT based formulations for ATPG of circuits having very large numbers of faults by implicitly eliminating detected faults. We solve a set of SAT problems whose constraints increase pure incrementally (here "pure" means never deleting constraints), and so the entire solving process can be very efficient, as all learnings obtained so far are valid in the following SAT problems. Experiments are performed on combinational parts of ISCAS89 circuits in their AIG (AND-Inverter Graph) representations. We have successfully generated the complete set of test vectors assuming that faults happen only at outputs of gates. Our ATPG techniques can also start with a given set of test vectors. If we start the ATPG processes with a set of test vectors for single stuck-at faults, we can obtain the set of additional test vectors required for multiple stuck-at faults. Results are a little bit surprising in the sense that we need very few additional test vectors for multiple faults, although the numbers of fault combinations are exponentially larger. As far as we know, for the first time, complete test vectors for all stuck-at faults for ISCAS89 circuits where faults happen only at outputs of gates in AIG representations of the circuits have been obtained.

In this paper, we provide a family of bounds for the rate at which the functions of many inputs can be computed in-network on general topologies. Going beyond simple symmetric functions where the output is invariant to the permutation of the operands, e.g., average, parity, we describe an algorithm that is analyzed to provide throughput bounds (both lower and upper) for the general functions. In particular, we analyze our algorithm when the function to be computed is given as a binary tree schema. Our lower bounds depend on schema parameters like the number of operands and graph parameters like the second largest eigenvalue of the transition matrix of simple random walk on network graph, the maximum and minimum degree of any node in the network. The lower bounding technique that we have used is based on the network flows and can capture general multi-commodity flow settings. Our proposed algorithm uses the well-known simple random walk on a network as its basic primitive for routing. We show that the lower bound obtained on the rate of computation is tight for the complete network topology, the hypercube and the star topology. We also present an upper bound on the expected latency of any data operand in terms of the height of schema, well-studied random walk parameter like the hitting time, and the relative distance from the critical data rate. For the computation time of symmetric functions on the random geometric graph under the gossip model, our approach achieves an order-optimal \(\widetilde{O}(n)\) time despite enforcing a binary tree schema for function computation. In general, Big-O notation represents an upper bound and \(\widetilde{O}\) hides \(\text {poly}\log n\) factors.

In this work we propose a novel concept called state tuple to represent the states of lines in a circuit for the generation of two pattern tests. The proposed approach is described in detail for generating robust two pattern tests for path delay faults in standard scan designs. Using the proposed approach we also report experimental results of a test generator for robust path delay faults in standard scan designs. The results show that the test generator achieves high efficiency with reduced implementation complexity.

Moving-type Preisach-derived models computing both the irreversible and the locally reversible components of the magnetization accurately characterize magnetic recording materials exhibiting hysteresis. Experimental results show that the derivative of the major remanent loop is not a symmetrical function of the applied field. It is shown that the complete moving hysteresis model can compute such an asymmetrical variation with a symmetrical Preisach function. It is also shown that this asymmetry is due to the reversible magnetization. Additional properties of moving-type models are also discussed.

We have proposed a method for identifying candidate single stuck-at faults based on the ambiguous test set (Takahashi et al., 2003). In this paper, we propose enhancing methods for diagnosing single/multiple stuck-at faults under BIST environment to reduce the number of candidate faults. The enhancing method uses the number of detections for candidate faults and the first detecting test to diagnose the candidate faults. Moreover, we propose an enhancing method for diagnosing multiple stuck-at faults by using test-pairs.

The present work focuses on a test design with self correcting features and with much higher efficiency for L1 cache modules. It is based on 2-state 3-neighborhood cellular automata (CA). The design ensures identification of the region of defective cache module in the Chip Multiprocessors (CMPs) and can memorize the fault while continuing with the test. Exploration of 3-neighborhood CA theory further strengthens the design towards a fault tolerant test structure. Self correction of the single stuck-at fault as well as the multiple stuck-at faults in the test structure has been envisaged. This fault tolerant test hardware achieves 100% accuracy in testing for single stuck-at fault whereas, the accuracy for multiple stuck-at faults is found to be 22%. As the design is developed around the 3-neighborhood CA, it becomes simpler as well as cheaper while considering VLSI implementation than that of the 5-neighborhood CA based design proposed in the literature.

Article Free Access Share on Delay fault coverage and performance tradeoffs Authors: William K. Lam View Profile , Alexander Saldanha View Profile , Robert K. Brayton View Profile , Alberto L. Sangiovanni-Vincentelli View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993Pages 446–452https://doi.org/10.1145/157485.164970Published:01 July 1993Publication History 89citation253DownloadsMetricsTotal Citations89Total Downloads253Last 12 Months17Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Effectiveness of single fault tests to detect multiple faults in parity trees