Interconnect-aware high-level synthesis for low power

Interconnects (wires, buffers, clock distribution networks, multiplexers and buses) consume a significant fraction of total circuit power. In this work, we demonstrate the importance of optimizing on-chip interconnects for power during high-level synthesis. We present a methodology to integrate interconnect power optimization into high-level synthesis. Our binding algorithm not only reduces power consumption in functional units and registers in the resultant register-transfer level (RTL) architecture, but also optimizes interconnects for power. We take physical design information into account for this purpose. To estimate interconnect power consumption accurately for deep sub-micron (DSM) technologies, wire coupling capacitance is taken into. consideration. We observed that there is significant spurious (i.e., unnecessary) switching activity in the interconnects and propose techniques to reduce it. Compared to interconnect-unaware power-optimized circuits, our experimental results show that interconnect power can be reduced by 53.1% on an average, while reducing overall power by an average of 26.8% with 0.5% area overhead. Compared to area-optimized circuits, the interconnect power reduction is 72.9% and overall power reduction is 56.0% with 44.4% area overhead.

Optimizing area and timing have long been considered to be the main design challenges in high-level synthesis. A lot of research has been conducted in this area and many techniques to improve performance have been suggested. However, as design applications become more power-sensitive, and with the emergence of portable devices that operate under stringent power constraints, power consumption surfaced as a major issue to be considered in the design and optimization processes. This work studies the effects of binding and scheduling on power consumption in high-level synthesis by analyzing unnecessary switching. The major contribution of this work is to reduce the unnecessary switching at the inputs of a circuit's functional units, referred to as spurious switching activities. For this purpose, all spurious and nonspurious switching inputs in a circuit were identified, and many techniques were studied to find the optimal register bindings without inducing any increase in the number of storage elements. Power reduction was attained through altering register bindings using a cool-down simulated annealing approach. To test these techniques, a high-level synthesis environment, "Eridanus", was developed and several benchmarks, consisting of various complexities, have been tested. Using the approach suggested in this work, spurious switching activity was reduced by 40% on average.

This paper deals with power minimization problem for data-dominated applications based on a novel concept called partially guarded computation. We divide a functional unit into two parts: MSP (Most Significant Part) and LSP (Least Significant Part) and allow the functional unit to perform only the LSP computation if the range of output data can be covered by LSP. We dynamically disable MSP computation to remove unnecessary transitions thereby reducing power consumption. We also propose a systematic approach for determining optimal location of the boundary between the two parts during high-level synthesis. Experimental results show about 10/spl sim/44% power reduction with about 30/spl sim/36% area overhead and less than 3% delay overhead in functional units.

Power efficiency has become a paramount concern in modern VLSI circuits, particularly for low-power applica tions. Flip-flops and clock distribution networks (CDNs) contribute significantly to dynamic power consumption, thus heavily impactingsystem performance. This paper proposes a novel Pulse-Triggered Flip-Flop (P-FF) architecture that incorporates an advanced pulse control mechanism combined with a NOR-based clock gating technique to address power inefficiencies. The proposed design minimizes the number of stacked NMOS transistors, employs conditional pulse enhancement during critical transitions, and strategically gates the clock to reduce unnecessary switching activity. Simulations conducted using Tanner EDA tools at a 250 nm CMOS technology node across a wide input voltage range (-1V to 5V) demonstrate that the proposed flip-flop achieves up to 89% reduction in power consumption compared to conventional flip-flop designs such as MHLFF, IMFF, and SECCER-FF. The results further highlight that the proposed P- FF provides superior dynamic power savings, reduced leaka ge, simplified structure, and robust performance across varying operating conditions. These characteristics make the proposed flip-flop an ideal candidate for next-generation low-power VLSI applications, including portable electronics, embedded systems, and high-performance computing platforms. Key Words: low power, CMOS, SECCER-FF, EDA, P-FF.

In this brief, we investigate and propose solutions for integrating the clock and power distribution networks all the way to circuit level. The aim is to reduce metal requirements, routing complexity, and power. The concept of an integrated power and clock distribution network (IPCDN) is proposed in order to eliminate the need for the global and local clock distribution networks. In IPCDN, a differential power-clock signal (Pwr_Clk) with a suitable dc voltage level and sinusoidal voltage-swing feeds the VDD ports in combinational and sequential elements. A clock buffer is used for sequential elements in order to extract a full-swing clock from the differential Pwr_Clk+ and Pwr_Clk- signals. IPCDN does not require any change to be made to the conventional combinational and sequential circuit design. The proposed elements of IPCDN, including the LC differential Pwr_Clk driver and the clock buffer, have been simulated using Taiwan Semiconductor Manufacturing Company 65-nm CMOS technology with a Pwr_Clk signal, a 1-V dc component, and 400-mV sinusoidal swing at a frequency of 5 GHz. In addition, the behavior of a master-slave flip-flop with IPCDN was investigated at extreme corners. Simulation results demonstrate correct functionality of all elements of the IPCDN. Comparing IPCDN to a buffered square-wave clock distribution network illustrates that, with a heavily loaded network, IPCDN achieves around 20% reduction in power. This percentage increases when the network capacitance is dominating.

Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study functional unit binding (or module assignment) given a scheduled data flow graph under a dual-V/sub dd/ framework. We assume that each functional unit can be driven by a low V/sub dd/ or a high V/sub dd/ dynamically during run time to save dynamic power. We develop a polynomial-time optimal algorithm for assigning low V/sub dd/ to as many operations as possible under the resource and time constraint, and in the same time minimizing total switching activity through functional unit binding. Our algorithm shows consistent improvement over a design flow that separates voltage assignment from functional unit binding. We also change the initial scheduling to examine power-latency tradeoff scenarios. Experimental results show that we can achieve a 21% power reduction when latency bound is tight. When latency is relaxed by 10 to 100%, the power reduction is 31 to 73% compared to the synthesis results for the case of single high V/sub dd/ without latency relaxation. We also show comparison data of energy consumption under the same experimental setting.

PurposeIn this work, an efficient architecture for memory built in self-test (MBIST) that incorporates a modified March Y algorithm using concurrent technique and a modified linear feedback shift register (LFSR)–based address generator is proposed.Design/methodology/approachBuilt in self-test (BIST) is emerging as the essential ingredient of the system on chip. In the ongoing high speed, high tech sophistication technology of the very large-scale integrated circuits, testing of these memories is a very tedious and challenging job, since the area overhead, the testing time and the cost of the test play an important role.FindingsWith the efficient service of the adapted architecture, switching activity is considerably cut down. As the switching activity is in direct proportion to the power consumed scaling down, the switching process of the address generator inevitably leads to the reduction in power consumption of the MBIST.Originality/valueTo improve the yield and fault tolerance of on-chip memories without degradation on its performance self-repair mechanisms can be implemented on chip.

With the development of fabrication, the capacities of application-specific integrated circuits (ASICs) that implement data-intensive applications are increasing as well. in high-level view, the results of functional units (FUs) and register allocation have a significant impact on power, thermal, area and timing etc., especially for data-dominated behaviors. Techniques for power minimization might be applied in different levels of the design hierarchy, but high-level synthesis (HLS) has attracted a special attention due to its inherent ability of better design space exploration. All kinds of methods for register optimization are presented in the recent past. This paper presents a new simultaneous FUs and register allocation method, which combining heuristic list scheduling algorithm and left-edge algorithm to optimize register number and power. From the experimental results, it shows that different FUs allocation results deliver an average 1.83 reduction in register number. And compared with traditional allocation method, we can obtain a 5.81% reduction in power consumption. In order to optimize area with the design demand, it will be at the expense of power dissipation, our design method also can achieve power-area balance.

Centralized controllers commonly used in high-level synthesis often cause long wires and high load capacitance and that is why critical paths typically occur on paths from controllers to data registers. However, conventional high level synthesis has focused on the delay of datapaths making it difficult to solve the timing closure problem during physical synthesis. This paper presents a hardware architecture with a distributed controller, which makes the timing closure problem much easier. It also presents a novel high-level synthesis flow for synthesizing such hardware through datapath partitioning and controller optimization. According to our experimental results, the proposed approach reduces the controller and interconnect delay by 20.3-27.4% and the entire critical path delay by 6.6~10.3% with 0.2~13.3% area overhead. Even without area overhead, it reduces the critical path delay by 5.8~10%.

VLSI circuits are perceived to dissipate extra power during testing when compared with that of the normal function. Drastic heat may reduce circuit consistency, shoot up package cost, and even cause permanent damage to the circuit under test. Thus minimization of test power has gained increased significance. This paper explores the avenues in power minimization during test application in CMOS VLSI circuits since power consumption during testing is high when compared to normal operation. Design of low transition Test Pattern Generators is one usual method adopted to reduce power consumption. In the Proposed Modified Low Transition Linear Feedback Shift Register, power dissipation during testing is reduced by minimizing the switching activity between successive test vectors by comparing the two consecutive test vectors and inserting random bit such that total number of transitions is reduced without affecting the randomness. Significant advantage of this method is reduced power consumption with reduced complexity when compared to other existing methods. Considering experimental results there is a significant reduction in power consumption up to 36.2% for ISCAS'85 combinational bench mark circuits and up to 10% for ISCAS'89 Benchmark sequential circuit with marginal increase in area overhead.

This paper presents a new algorithm on lower-power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. It results in increasing the area of spurious switching activity region, and further reducing the switching activity with gated-clocks during trace-back operation. With the SYNOPSYS power estimation tool, DesignPower, our experimental result shows on the average 40% reduction in power with the same latency at a cost of 23% increase in area against the trace-back unit introduced by Truong et al. (1992). The proposed survivor memory scheme can be applied to the digital communication systems for targeting low power consumption.

This paper proposes a technique for dynamic power reduction of pipelined processors. Pipelined processors frequently insert NOP instruction to the pipe for generating delay or resolving dependency. Our study shows that the percentage of power consumed by NOP instructions in a pipelined processor is significant. This article studies the detail behavior of NOP instruction and proposes a technique for eliminating unnecessary transitions that are generated during execution of NOP instructions. Initial results demonstrate up to 10% reduction in power consumption for some benchmarks at a cost of negligible performance (almost zero) and area overhead (below 0.1%).

Conventional high-level synthesis algorithms treat specification operations as atomic elements that are executed in one or several consecutive cycles and over one functional unit. However, in most specifications there exist different operations, in function of their type, representation, and width that handled at different decomposition levels may produce better designs. In this way, most arithmetic operations can be decomposed into smaller operations applying several arithmetical properties. Different decompositions can be performed, in function of the pursued objective: performance improvement, area reduction, or power consumption reduction. In this paper we propose a pattern-based design methodology able to treat every operation at its most appropriate decomposition level. It produces reduced datapaths while meeting the specified time constraints. In comparison to conventional algorithms the amount of area saved averages 40%.

Reducing resource usage is one of the most important optimization objectives in behavioral synthesis due to its direct impact on power, performance and cost. The datapath in a typical design is composed of different kinds of components, including functional units, registers and multiplexers. To optimize the overall resource usage, a behavioral synthesis tool should consider all kinds of components at the same time. However, most previous work on behavioral synthesis has the limitations of (i) not being able to consider all kinds of resources globally, and/or (ii) separating the synthesis process into a sequence of optimization steps without a consistent optimization objective. In this paper we present a behavioral synthesis flow in which all types of components in the datapath are modeled and optimized consistently. The key idea is to feed to the scheduler the intentions for sharing functional units and registers in favor of the global optimization goal (such as total area), so that the scheduler could generate a schedule that makes the sharing intentions feasible. Experiments show that compared to the solution of minimizing functional unit requirements in scheduling and using the least number of functional units and registers in binding, our solution achieves a 24% reduction in total area; compared to the online tool provided by c-to-verilog.com, our solution achieves a 30% reduction on average.

A new method that integrated high level synthesis and floorplan are proposed to reduce the total power dissipation. Function units are sorted into several clusters according to their working voltages. Floorplan are executed with the information of cluster gained from high level synthesis, and then the high level synthesis resolutions are adjusted iteratively with the interconnect information and switching activity gained from floorplan. Not only function unit power and interconnect power, but also the voltage converting power can be reduced in our method. Experimental results indicate that, under the given resource and latency constrains, the interconnect power, level convert power and total power of our method can be reduced by 30.4%, 35.1% and 22.9% respectively.