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Invited talk: A short-time implementation for a high-performance binarized deep convolutional neural network on an FPGA

  • May 1, 2017
  • Hiroki Nakahara
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Abstract

A pre-trained convolutional deep neural network (CNN) is a feed-forward computation perspective, which is widely used for the embedded systems, requires highly power and area efficiency. Also, with a rapid growth of the CNN techniques, a short time-implementation is a mandatory. In this talk, I introduce a binarized CNN on an FPGA which treats only binary 2-values (+1/−1) for the inputs and the weights. In this case, the multiplier is replaced into an XNOR circuit instead of a dedicated DSP block. For hardware implementation, using binarized inputs and weights is more suitable. Additionally, I show the optimization techniques for the binarized one for the FPGA implementation. Next, I propose a framework for an FPGA realization of the binarized CNN by using a high-level synthesis. Our developed framework supports a modern CNN frameworks, such as a Caffe, Theano, TensorFlow, and Chainer. Thus, we can implement the high-performance CNN on the FPGA with a short time. Finally, I show the comparison of the conventional implementations, then, introduce the applications using the binarized CNN on the FPGA.

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