Logic simulation system using simulation processor (SP)

During 1979, CERN began to evaluate how interactive computer graphics displays could aid the analysis of high-energy physics experiments at the new Super Proton Synchrotron collider. This work led to PIONS, a 3D graphics system, which features the ability to store and view hierarchical graphics structures in a directed-acyclic-graph database. It is possible to change the attributes of these structures by making selections on nongraphical information also stored in the database. PIONS is implemented as an object-oriented message-passing system based on Small Talk design principles. It supports multiple viewing transformations, logical input devices, and 2D and 3D primitives. The design allows full use to be made of display hardware that provides dynamic 3D picture transformation.

Ferroelectric vortex in multiferroic materials has been considered as a promising alternative to current memory cells for the merit of high storage density. However, the formation of regular natural ferroelectric vortex is difficult, restricting the achievement of vortex memory device. Here, we demonstrated the creation of ferroelectric vortex-antivortex pairs in BiFeO3 thin films by using local electric field. The evolution of the polar vortex structure is studied by piezoresponse force microscopy at nanoscale. The results reveal that the patterns and stability of vortex structures are sensitive to the poling position. Consecutive writing and erasing processes cause no influence on the original domain configuration. The Z4 proper coloring vortex-antivortex network is then analyzed by graph theory, which verifies the rationality of artificial vortex-antivortex pairs. This study paves a foundation for artificial regulation of vortex, which provides a possible pathway for the design and realization of non-volatile vortex memory devices and logical devices.

Degradation of lithographic pattern fidelity is a major cause of yield loss in VLSl manufacturing. A general methodology for full-chip analysis and improvement of yield loss due to lithographic effects is proposed The approach is based on: a) extraction of pattern fidelity statistics using a full-chip layout engine, b) full-chip optical proximity correction (OPC) to improve pattern reproduction, and c) estimation of yield losses due to line variability, using transistor sensitivity to pattern registration obtained from physical transistor modeling. As a result, yield estimates related to either pattern reproduction fidelity or transistor parametric data variations (such as leakage or drive current) are generated. The method is efficient and well suited for application to modern VLSI designs of memory or logic devices.

With the rapid development of computer hardware and software technology, the hardware size and performance of embedded system have been greatly improved, accordingly, the complexity and size of the embedded system software have also doubled.However, the particularity of the embedded system requires the hardware system and application software operated on it to be concise and efficient, stable and reliable.This makes the proportion of the software development in the whole embedded system development higher and higher.The software quality plays a crucial role in the whole product quality .As a result, we urgently need a testing method and tools for embedded field to improve software quality and reliability, shorten the software development period and reduce development costs.Under this background, this paper goes into the testing technology of embedded electronic system software and applies the research results to testing.From the actual needs, it goes into the software metrics technology and applies it to vehicle electronic system testing.

Recently, several systems based on reconfigurable logic have been designed and built. These systems permit arbitrary digital logic functions to be configured in hardware. This ability to dynamically configure such circuits promises to provide the flexibility of a software based system with the performance of custom hardware. This dissertation proposes a high level language approach to programming reconfigurable logic based machines. This approach uses a data parallel variant of the Clanguage. To support this high level language approach, a novel reconfigurable logic device is described. These devices are in turn interfaced to a memory system and used to perform computation. To demonstrate the validity of this approach, several computationally intensive algorithms are implemented and simulated. Among these algorithms are cellular automata, image processing, neural networks, the Mandelbrot set and the Fourier transform. In addition, selected portions of the Livermore FORTRAN kernels are simulated. Estimates of performance and required system resources are reported for each algorithm.

Spintronics presents great promise for efficient processing and storage of information in the post-Moore era, thanks to its attributes of non-volatility, excellent integration-density, near-unlimited endurance and compatibility with CMOS process-technology. Today's state-of-the-art EDA tools primarily use AND-Inverter Graphs (AIGs), Majority-Inverter Graphs (MIGs) and XOR-Majority Graphs (XMGs) for representing any complex Boolean logic. To be able to utilize the existing EDA tools for implementing spin-based logic circuits, it is important that the logic primitives in these data structures can be natively realized by spin devices. This paper demonstrates how the XMGs synthesized by EDA flows can be more-efficiently mapped to spintronic fabric using a novel domain wall motion-based XOR device. We develop a device-to-system simulation-framework to precisely evaluate the post-mapping (to domain-wall gates) performances of synthesized networks. Our study over several challenging benchmark-suites shows that the use of this XOR-gate enables the efficient mapping of XMGs while improving the {size, depth, size·depth, energy, EDP} performances of the network by averages of {31.54%, 19.00%, 41.56%, 38.03%, 45.47%} over those of mapped MIGs.

A design for optoelectronic multiple-value logic circuits that uses bistable laser diodes or light-emitting diodes is reported. In this multiple-valued logic design, an optoelectronic tristable switching circuit, or light-current mirror, in which two bistable light-emitting diodes are connected in parallel serves as the basic logic element. Five ternary logic implementations: Complement. Max(x, y), Min(x, y), Cycle, and Literals, have been demonstrated experimentally. Furthermore, any ternary logic function can be generated with the light-current mirror and the logic primitives.

Mission-critical systems require increasing capability for fault handling and self-adaptation as their system complexities and inter-dependencies increase. Organic Computing (OC) architectures utilize biologically-inspired self-x properties which include self-configuration, self-reorganization, and self-healing which comprise the focus of this paper. To provide OC architectures with sufficient capability for exhibiting self-adaptive behavior, reconfigurable logic devices offer a suitable hardware platform. SRAM-based Field Programmable Gate Array (FPGA) logic devices can realize self-adaptation within their reconfigurable logic fabric using Evolvable Hardware techniques based on crossover, mutation, and iterative selection with intrinsic fitness assessment of the underlying hardware resources. In this paper, a dual-layer Organic Computing architecture called the Organic Embedded System (OES) is prototyped on a Xilinx FPGA reconfigurable fabric and assessed for maintainability metrics of completeness of repair, repair time, and degraded throughput during the repair phase. The approach used extends a widely known generic OC platform consisting of two layers: the Functional Layer and the Autonomic Layer. The Autonomic layer contains Autonomic Elements (AEs) that are responsible for correct operation of the corresponding Functional Elements (FEs) present on the Functional Layer. Innovations include autonomously degraded online throughput during regeneration, spare configuration aging and outlier driven repair assessment, and a uniform design for AEs despite the fact that they monitor different types of FEs. Using the OES approach; a malfunctioning or faulty AE among the population can be distinguished by its discrepant performance. The OES approach is implemented using high-level Hardware Description Language (HDL) which directs a Supervisor Element (SE) to function as a fault management unit through the collection of AE information. Experimental results show that the OES Autonomic Layer demonstrates 100% faulty component isolation for both FEs and AEs with randomly injected single faults. Using logic circuits from the MCNC-91 benchmark test set, throughput during repair phases averaged 75.05%, 82.21%, and 65.21% for the z4ml (2-bit adder), cm85a (high fan-in combinational logic), and cm138a (balanced I/O combinational logic) circuits respectively under stated conditions.

Despite the benefits that optics and photonics have brought to improving communications, there remains a lack of commercialized optical computing devices and systems, which reduces the benefits of using light as an information-carrying medium. We are developing architectures and designs of photonic logic gates for creating larger-scale functional photonic logic circuits. In contrast to other approaches, we are focusing on the development of logic devices which can be cascaded in arbitrary ways to allow for more complex photonic integrated circuit design. Additionally, optical computing often uses on-off keying, which fails to take advantage of denser encoding schemes often used to optically transmit data. We propose that devices that operate on phase-shift keying will not only be more efficient, but easier to cascade. To achieve the goal of cascadable devices operating on phase-shift keying, we have designed a plasmonic waveguide logic device using inverse design tools. These tools have allowed us to create a device with an arbitrary topology that has increased performance and reduced footprint compared to a conventional device with the same operation. In addition, inverse design simplifies the process of designing devices that operate with phase-shift keying, which can become complicated with conventional design methods. In order to implement inverse design tools for plasmonic devices and phase-shift keying, we used fully 3D FDTD simulations. We compare the inverse-designed devices to more conventional devices in order to characterize their performance.

This study presents the development of a mechatronic device for an additively manufactured Pneumatic Artificial Muscle (PAM) rehabilitation orthosis. Within this scope, the system's electro-pneumatic, mechanical, control, and software designs have been designed and implemented. The device, intended to directly interact with both patients and therapists within the bio-mechatronic process, is equipped with an intuitive graphical user interface (GUI). Utilizing a FlexSensor to measure hand flexion/extension angles, the device employs a solenoid valve, along with a trigger relay, for the inflation and deflation of the orthosis. During the electronic design phase, challenges such as interference and latency were mitigated through the implementation of isolations in the design. Employing a PD (Proportion-Derivative) control loop on the ATmega328 microcontroller, control parameters were determined empirically. By excluding a compressor pump inside the device, a lightweight, portable, and cost-effective system was accomplished. While potential enhancements discussed in the conclusion will be considered in future studies, the current prototype effectively fulfills the project objectives.

Recent research on NEM devices for logic and memory applications has been reviewed from the perspective of monolithic 3D (M3D) heterogeneous integration. In addition, the backgrounds of M3D CMOS-NEM reconfigurable logic (RL) circuits are described in detail. Moreover, 65-nm process based M3D CMOS-NEM RL circuits were proposed. It is predicted that proposed M3D CMOS-NEM RL circuits will exhibit 4.6x higher chip density, 2.3x higher operation frequency and 9.3x lower power consumption than CMOS-only ones (tri-state buffer case) for tile-to-tile operation.

The printing industry is undergoing rapid change with the advent of new technology. The laser provides a tool with which direct exposure platemaking may become a reality. To achieve direct exposure of a complete page, lineart and halftone graphics must be recorded in addition to text. Much of the technology to achieve the desired result is available today, usually seen in other applications. All aspects of text processing, data base management and typesetting must be considered in the design of a laserdriven exposure device. There has been an evolution in both software systems and hardware elements that will eventually make the laser typesetter or platemaker a practical reality.

1. The possibility of effective optical control of the shape of volt-ampere characteristics of avalanche transistors has been demonstrated. 2. Test samples of avalanche phototransistors have been fabricated and investigated. The parameters of the investigated samples are in good agreement with the calculated values. 3. The high speed of response of avalanche phototransistors for optical triggering of the relaxation circuits has been substantiated experimentally. In particular, such circuits were triggered by short pulses of coherent infrared radiation obtained from lasers. 4. The use of optically controlled avalanche transistors opens up new possibilities in the design of high-speed pulse and logical opticoelectronic devices.

Many high-technology products currently manufactured are affected adversely if contamination is deposited in or on the product during manufacture or use. Contamination can be defined as any condition, material, process, or effect that can degrade quality, performance, or yield for any product. The product can be an electronic device, an optical or mechanical assembly, a pharmaceutical product or device, or essentially any modern “high-technology” product. The product can also be a simple system, such as a food item or plant that can be affected adversely by airborne bacteria. A contaminant can be a particulate or a gaseous material; it can be a harmful electric field or an excessive vibration level. It can be the condition of excessive moisture (relative humidity) in an assembly area, or it can be a high light flux at harmful wavelengths in a lithographic operation. It can be an excess of lubricant in a precise mechanical device, or it can be a condition of inadequate lubrication. An examination of an ultralarge-scale integrated (ULSI) semiconductor device manufacturing requirement might result in the conclusion that the entire manufacturing operation must use ultraclean technology (Ohmi 1988). As a strong example, regarding the design and operation of present-day logic and memory devices used in computers, it can be concluded that contamination control is a vital necessity, without which no computer or any of the many microprocessor-controlled devices in our modern world would be operating today. The dimensions of the circuitry used in these devices simply does not allow operation if the particulate contaminants found in “normal” air were to deposit upon these devices during the manufacturing process. The manufacturer must not only control particulate and vapor contamination but also control exposure to high-energy conditions and excessively variable thermal conditions, ensure freedom from vibration, and eliminate excessive process variations. These precautions are required during the manufacturing operation, during storage, and, in many cases, during product operation.

Patterned magnetic nanowires are extremely well suited for data storage and logic devices. They offer non-volatile storage, fast switching times, efficient operation and a bistable magnetic configuration that are convenient for representing digital information. Key to this is the high level of control that is possible over the position and behaviour of domain walls (DWs) in magnetic nanowires. Magnetic random access memory based on the propagation of DWs in nanowires has been released commercially, while more dynamic shift register memory and logic circuits have been demonstrated. Here, we discuss the present standing of this technology as well as reviewing some of the basic DW effects that have been observed and the underlying physics of DW motion. We also discuss the future direction of magnetic nanowire technology to look at possible developments, hurdles to overcome and what nanowire devices may appear in the future, both in classical information technology and beyond into quantum computation and biology.