Low-complexity, full-resolution, mirror- switching digital predistortion scheme for polar-modulated power amplifiers

We have demonstrated a frequency multiplier-based multiplying transmitter (MT) architecture, which shows the transmission of wideband modulated signals from the lower frequency band to the millimeter-wave (mm-wave) through the frequency multiplier directly is a viable option. To compensate for the severe nonlinear distortions exhibited by the frequency multiplier in a more efficient way, a two-stage cascaded digital predistortion (DPD) scheme with constrained feedback bandwidth is proposed. The complexity-reduced generalized memory polynomial (GMP) and $N$ th-order power/root module are used for nonlinear behavioral modeling. Furthermore, the spectral extrapolation and band-divided (BD) modeling methods are employed to achieve more accurate linearization performance of the frequency multiplier over the limited feedback bandwidth. The MT experimental system with an active frequency quadrupler at the Q-band was set up to evaluate the linearization capacity of the proposed BD $N$ th-order cascaded complexity-reduced GMP (BD-N-CGMP) DPD scheme. In the test for 24-MHz bandwidth 16 quadrature amplitude modulation (QAM) signal, the frequency quadrupler’s linearized output at 48.6 GHz with error vector magnitude (EVM) of 1.94% and adjacent channel power ratio (ACPR) of −47.2 dBc could be achieved, even when the feedback bandwidth was limited from 480 to 78 MHz. This demonstrated system significantly decreased the requirement of the digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) sampling rate, and showed promising performances for future MT architecture at mm-wave and sub-terahertz (sub-THz) frequencies with large signal bandwidth.

This paper presents the Direct Current (DC) power budget analysis and Radio Frequency (RF) frontend system design considerations of a medium Power Amplifier (PA) with average power output of 1watt. The PA system analysis is performed in a simulation environment for three linearization usage scenarios such as, Back-off, Digital Pre-Distortion (DPD) and Analog Pre-Distortion (APD) schemes. In the Back-off mode, the total RF frontend power consumption is 35.87 watt and with the usage of DPD topology the power consumption is 32.76 watt while with APD topology, the power consumption is 23.74 watt. The APD topology considers a Commercial off the Shelf (COTS) design topology with using moderately non-linear PA device operation. As compared to the back-off operation, the DPD scheme has got a 8.6% estimated relative power saving and the APD provides an estimated relative power saving of 33.8%.

An adaptive digital predistortion scheme, based on the amplitude-and-phase predistortion concept, is considered for the linearisation of microwave power amplifiers in high-data-rate radio relay links. The algorithm is thoroughly assessed and compared to a digital predistortion scheme recently proposed in the literature, assuming linearisation accuracy, adaptation speed and implementation complexity as merit criteria. The proposed predistorter proves to be considerably faster than the other scheme, though exhibiting approximately the same accuracy and a reduced complexity.

We consider digital predistortion (DPD) for linearizing power amplifiers (PAs) of hybrid MIMO systems with subarrays. Designing such a DPD scheme is difficult because one DPD should linearize all PAs of a subarray whose beamforming coefficients are time-varying. We develop an adaptive DPD technique for each subarray based on direct learning method minimizing the sum of squared errors between the input and output signals of PAs. Use of the least mean square (LMS) Newton algorithm is proposed to adaptively control the DPD parameters. It is shown that the proposed DPD can simultaneously linearize multiple PAs in a subarray irrespective of its beamforming coefficients. Computer simulation results demonstrate that the proposed scheme can perform better than an alternative scheme that designs the DPD based on one of the PA outputs and uses the resulting DPD for all PAs of the subarray.

A digital pre-distortion (DPD) scheme based on an adaptive-memory-length look-up table (AML-LUT) is proposed and experimentally demonstrated in a four-level pulse amplitude modulation (4-PAM) underwater optical wireless communication (UOWC) system. By implementing adaptive memory length for each pattern in the AML-LUT-based DPD, the size of the AML-LUT can be significantly reduced without sacrificing performance compared to both the full-size LUT and the multi-symbol simplified look-up table (MSS-LUT)-based DPDs. The performance of the proposed AML-LUT-based DPD is experimentally evaluated for a 625 Mbit/s 4-PAM UOWC over 1 m transmission length. Experimental results show that compared with the full-size LUT with a memory length of 7 (LUT-7)-based DPD, the proposed AML-LUT-based DPD (i) incurs a marginal power penalty of 0.5 dB at both the 7% hard-decision forward error correction (HD-FEC) and KP4-FEC threshold limits, while simultaneously reducing the implementation complexity (i.e., the LUT size) by 93%; (ii) achieves comparable transmission performance compared to the MSS-LUT-based DPD, while reducing the implementation complexity by 89%; and (iii) shows great potential for high-speed, low-complexity and memory-efficient intensity modulation and direct detection (IM/DD) UOWC and short-reach optical interconnects.

This paper proposes a digital predistortion (DPD) scheme devised to improve the quality of wideband digitally modulated signals generated using frequency doubler based high frequency sources. The proposed DPD consists of two modules, which are configured to tackle the nonlinearity exhibited by frequency doublers when driven with high peak-to-average-power ratio (PAPR) signals. The first module is a memoryless (ML) polynomial describing function with a square root basis to mitigate the squaring transformation of the input envelope signal to the frequency doubler. The second module consists of a pruned Volterra-series based model, which is incorporated to mitigate residual distortions. The proposed DPD scheme was validated by linearizing an active frequency doubler with its output centered at 25 GHz when stimulated with orthogonal frequency division multiplexing signals with modulation bandwidths of 160 MHz and 320 MHz, and PAPRs of 8.6 dB. When both modules of the proposed DPD scheme are set to be ML with nonlinearity orders of 4 and 6, the linearized frequency doubler exhibited normalized mean squared errors (NMSEs) of −28 dB, −26 dB and adjacent channel power ratios (ACPRs) of 50/47 dBc, 42/39 dBc for modulation bandwidths of 160 MHz and 320 MHz, respectively. By only adding memory distortion terms to the second module, the NMSEs significantly decreased from −28 dB to −35 dB for the 160 MHz case and from −26 dB to −32 dB for the 320 MHz case. For both cases, the ACPRs became more balanced after adding memory terms to the second module.

We consider the design of a digital predistortion (DPD) scheme when there is a crosstalk between a local oscillator (LO) and a power amplifier (PA) called LO self-coupling. We first develop a baseband equivalent model for a direct conversion transmitter afflicted by LO self-coupling. Based on this model, a two-stage process, consisting of a feedback equalizer (FBEQ) and DPD, is proposed for the joint compensation of PA nonlinearity and LO self-coupling. The advantage of the proposed DPD over conventional DPD is demonstrated through computer simulation.

High-symbol-rate coherentoptical transceivers suffer more from the critical responses of transceiver components at high frequency, especially when applying a higher order modulation format. We recently proposed a neural network (NN)-based digital pre-distortion (DPD) technique trained to mitigate the transceiver response of a 128 GBaud optical coherent transmission system. In this paper, we further detail this work and assess the NN-based DPD by training it using either a direct learning architecture (DLA) or an indirect learning architecture (ILA), and compare performance against a Volterra series-based ILA DPD and a linear DPD. Furthermore, we deliberately increase the transmitter nonlinearity and compare the performance of the three DPDs schemes. The proposed NN-based DPD trained using DLA performs the best among the three contenders. In comparison to a linear DPD, it provides more than 1 dB signal-to-noise ratio (SNR) gains at the output of a conventional coherent receiver DSP for uniform 64-quadrature amplitude modulation (QAM) and PCS-256-QAM signals. Finally, the NN-based DPD enables achieving a record 1.61 Tb/s net rate transmission on a single channel after 80 km of standard single mode fiber (SSMF).

In this paper, we present a low-power high-performance digital predistorter (DPD) for the linearization of wideband RF power amplifiers (PAs). It is based on the novel FIR memory polynomial (FIR-MP) predistorter model, which significantly augments the performance of the conventional memory polynomial predistorter with the use of complex baseband digital FIR filter prior to the memory polynomial. The adjacent channel leakage ratio (ACLR) performance comparison between the conventional MP and the proposed FIR-MP is done based on simulations with multi-carrier modulated signals of 20 and 80 MHz bandwidths. The PA models used for the simulations are extracted from the measurements of a commercial $$1\,\hbox {W}$$ GaAs HBT PA. At the ideal system-level simulations, the improvements in ACLR over the conventional MP are 7.2 and 15.6 dB, respectively, for 20 and 80 MHz signals. The choice of selection of various parameters of the predistorter along with the subsequent digital-to-analog converter (DAC) is presented. The impact of fixed-point representation is assessed using ACLR metrics, which shows that a wordlength of 14 bits is sufficient to obtain ACLR beyond $$45\,\hbox {dBc}$$ with a margin of $$10\,\hbox {dB}$$ . The proposed predistorter is synthesized in $$28\,\hbox {nm}$$ fully-depleted silicon-on-insulator (FDSOI) CMOS process. It is shown that with a fraction of the power and die area of that of the MP a huge improvement in ACLR is attained. With an overall power consumption of 8.2 and 88.8 mW, respectively, for 20 and 80 MHz signals, the FIR-MP DPD proves to be a suitable candidate for small-cell base station PA linearization.

ABSTRACTThis work presents a digital predistortion (DPD) scheme to linearize power amplifiers (PAs) using a recurrent neural network called Nonlinear AutoRegressive with eXogenous input model (NARX) neural network (NARXNN). The architecture of the NARXNN is based on a class of discrete‐time nonlinear system named NARX. Its topology has embedded memory at the input and output of the neural architecture, which allows an efficient linearization of PAs. To show the benefits of the DPD with NARXNN, a commercial PA is fed with a long term evolution signal at 2.0 GHz with 10 MHz of bandwidth. Our experimental results show an adjacent channel leakage ratio improvement of 24 dB. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:2137–2142, 2015

This article first analyzes the nonlinear behavior of frequency-multiplier (FM)-based radio frequency (RF) beamforming transmitters TXs) over a wide range of steering angles. Then, based on this analysis, a digital predistortion (DPD) scheme is proposed to linearize FM-based TX arrays. Specifically, a dual-input behavioral model of FM-based TX arrays is derived. This dual-input model is then transformed into an angle-dependent single-input–single-output (SISO) model. Next, the effect of load modulation on FM nonlinearity is studied using a circuit-inspired behavioral model, and a very distinctive feature is revealed. Notably, it is shown that FM-based RF beamforming arrays have reduced sensitivity to load modulation when compared to last-stage power-amplifier (PA)-based arrays. This is first validated in simulation using a frequency doubler and PA terminated with load impedances extracted from an 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 8 electromagnetically simulated array. Furthermore, experimental results are obtained using a 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 2 planar frequency-doubler-based RF beamforming TX operated at 28 GHz and driven with up to 400-MHz-wide orthogonal frequency-division multiplexing (OFDM) signals where the subcarriers are modulated using up to 256-QAM. It is experimentally demonstrated that a single set of SISO DPD coefficients can significantly improve the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) over a wide steering range. Specifically, for the case of a 100-MHz signal, the ACPR and EVM improved from 20 dBc and 23% to, at worst, 48 dBc and 1%, respectively, when the array is steered from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-40^\circ $ </tex-math></inline-formula> to 40° and measured along the main beam direction. In light of the FM-based arrays reduced sensitivity to load modulation, this article also investigates different TX observation receiver (TOR) methods for DPD function training, namely, far-field-based TOR, coupler-based TOR, and single-element-based TOR, and their impacts on the linearizability of the FM-based RF beamforming TXs.

This paper reports a novel digital predistortion (DPD) scheme for concurrent tri-band power amplifier (PA). The proposed three-dimensional tri-band DPD is based on the analysis of crosstalk between the fundamental frequencies, their harmonics and intermodulation products due to the nonlinearity exhibited by the tri-band PA. The DPD performance is validated using a broadband PA driven concurrently with LTE, WIMAX, and WCDMA signals centered at 2.14 GHz, 2.425 GHz, and 2.655 GHz, respectively.

High frequency (HF) transmitters implemented with the multi‐octave power amplifier (PA) are always faced with the problem of interfering harmonics because of the nonlinearity of the PA. In this paper, the harmonic cancelation digital predistortion (HC‐DPD) scheme is proposed and well discussed to cancel the in‐band intermodulation distortion (IMD) as well as out‐of‐band harmonics at the same time. With the digital filter‐less scheme, the bulky and lossy filter banks can be removed. Nonlinear models are first utilized to approximate the nonlinear behavior of the HF PA and compared in terms of the model accuracy. Then, the learning architecture, model identification, and feedback compensation of the HC‐DPD scheme are detailed discussed. Finally, a series of simulations and experiments demonstrated the effectiveness of the proposed nonlinear models and linearization algorithms.

We have developed a new adaptive digital predistortion (DPD) linearization technique based on analog feedback predistortion (FBPD). The lookup-table-based feedback input can remove the bandwidth limitation of the feedback circuit related to the loop delay, and suppress feedback oscillation by accurate digital control of the feedback signal. Moreover, the predistortion (PD) signal can be extracted very efficiently. By combining the feedback linearization and DPD linearization techniques, the performance of the predistorter is enhanced significantly compared to the conventional DPD. To clearly visualize the characteristics of digital FBPD (DFBPD), we have compared it to the conventional DPD based on the recursive least square algorithm using Matlab simulation. The results clearly show that the new method is a good linearization algorithm, better than a conventional DPD. For the demonstration, a Doherty power amplifier with 180-W peak envelope power is linearized using the proposed DFBPD. For a 2.14-GHz forward-link wideband code-division multiple-access signal, the adjacent channel leakage ratio at 2.5-MHz offset is -58 dBc, which is improved by 15 dB at an average output power of 43 dBm

The paper presents the results of laboratory studies on influence of DC transistor operating conditions both on power amplifier (PA) linearity and effectiveness of digital predistortion procedure. The impact of DC operating conditions of 10 W GaN HEMT power amplifier on nonlinearity factors without and with digital predistortion (DPD) were investigated. The obtained results show that there is an additional improvement in adjacent channel leakage ratio (ACLR) of the order of a few dB only by an increase in the quiescent drain current of PA transistor. However, some noticeable improvement of ACLR with significant increase in PA power added efficiency (PAE) is obtained for PA with digital predistortion.