Low-Power UART Architecture with Integrated SECDED for Reliable Asynchronous Communication

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit precomputation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weightcolumn code during the write operation and is designed by replacing 0’s with 1’s at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the oddweight-column code, the implementation based on the proposed SEC-DED code with check bit precomputation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

As the size of on-chip SRAM caches is increasing rapidly and the physical dimension of the SRAM devices is decreasing, reliability of caches is becoming a growing concern. This is because with increased size of caches, the likelihood of radiation-induced soft faults also increases. As a result, information redundancy in the form of Error Correcting Codes (ECC) is becoming extremely important, especially to protect the larger sized last level caches (LLCs). In typical ECCs, extra redundancy bits are added to every row to detect and correct errors. There is additional encoding (while writing data) and decoding (while reading data) procedures required as well. In caches, these additional area, power and latency overheads need to be minimized as much as possible. To address this problem, we present in this paper Parity++: a novel unequal message protection scheme for last level caches that preferentially provides stronger error protection to certain "special messages". This protection scheme provides Single Error Detection (SED) for all messages and Single Error Correction (SEC) for a subset of messages. Thus, it is stronger than just a basic SED parity and has much lower parity storage overhead (4X lower for a 64-bit memory) and lower error detection energy than a traditional Single Error Correcting, Double Error Detecting (SECDED) code. We also evaluate Parity++ with a memory speculation procedure that can be used with any ECC scheme to hide the decoding latency while reading messages when there are no errors.

An error correcting code has teen developed for the serial transmission of digital data over a fiber optic link. It is a 96 bit block code, with single bit error correction and double bit error detection. Each block consists of eight 8b/lOb coded symbols and sixteen error correction bits. The coded data has a maximum run length of 4, minimum transition density of 25%, and a digital sum variation of +1- 4 bits.A chip set implementing the code has been demonstrated in an experimental link running at 1 Gbit/s (1.5Gbaud).INTRODUCTIONCoding is required for fiber optic data links to transform unencoded data into a serial sequence withknown properties. Since the clock must be recovered fromthe serial data, a high transition density andshort run length are desirable. Most wide bandwidth amplifiers are AC-coupled, dictating that the serialdata have minimal DC content.Forward Error Control (FEC) block codes have been widely used in magnetic media and dynamicRAM systems to improve the effective error rate. At the expense of some channel bandwidth (or storagespace), the error rate may be improved by including check codes that allow detection and correction oferrors.The code described here combines an 8b/lOb code with a Single Error Correcting-Double Error De-tecting (SEC-DED) block code while maintaining the desirable serial data characteristics.8b/IOb CODE

The authors have designed and characterized a single-error-correcting (SEC), double-error-detecting (DED) code applicable to the STS-1 SONET format. They show that if two of the presently unallocated bytes in the path overhead field of STS-1 are assigned for error-correction coding (ECC), a (6208, 6195) shortened extended Hamming code can be implemented using as few as 660 gates plus a 1-kbyte RAM IC, achieving (O8.6*10/sup -3/ P/sub 2//sup 2/) BER reduction with 139 mu s of signal delay. The authors explain how the existing BIP-8 error-monitoring byte of the STS-1 format could be integrated with the proposed ECC so that a net allocation of only one new STS-1 overhead byte is required for both error monitoring and error correction. The implementation method is such that all path, line, and section overhead functions in SONET can be performed at intermediate sites without requiring ECC decoding. The authors consider application alternatives and describe the forward-error-correction (FEC) circuit design and trial results. System issues are covered, including network delay, effects of error extension on BER, addition of double-error detection, performance monitoring, and options for intelligent network control and management of FEC functions. Codes related to their path-level design that are applicable to a number of other strategies for applying FEC in SONET are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A main characteristic of the Internet of Things networks is the large number of resource-constrained nodes, which, however, are required to perform reliable and fast data exchange; often of critical nature; over highly unpredictable and dynamic connections and network topologies. Reducing the number of message exchanges and retransmission of data, while guaranteeing the lifetime of the data session duration as per service requirements are vital for enabling scenarios such as smart home, intelligent transportation systems, eHealth, etc. This paper proposes a novel theoretical model for the discovery, linking and interpretation of nodes in unstructured and resource-constrained network environments and their interrelated and collective use for the delivery of smart services. The model is based on a basic mathematical approach, which describes and predicts the success of human interactions in the context of long-term relationships and identifies several key variables in the context of communications in resource-constrained environments. The general theoretical model is described and several algorithms are proposed as part of the node discovery, identification, and linking processes in relation to the key variables. The algorithms are each evaluated by simulations to determine which parameters are key for optimal node grouping.

A code is presented which is designed to protect a 64 bit word, consisting of 8 bytes of 8 bits each, against both byte errors and single bit errors occurring in computer memories. Two check bytes are appended to give an overall length of 80 bits. The code then provides the often studied SEC-BED-DED level of error protection; that is, single error correction, byte error detection and double error detection are available simultaneously. In addition, the code detects a byte error together with a single random error occurring concurrently in another byte. Some implementation issues such as systematic versus separable encoding are considered. >

Smart homes are a strong match for the characteristics of product-service systems (PSSs), but practitioners lack the knowledge necessary to approach their designs from a systemic perspective. Positing that smart home appliances (SHAs) are the building blocks of smart homes as competitive PSSs, this article investigates the attributes of SHAs as design elements and the advantages of PSSs as design goals. Based on systematic literature reviews and interviews with SHA experts in South Korea, the authors propose a revised set of SHA attributes and discuss the two focal areas for developing competitive PSSs with SHAs: smartness for personalized user experiences and smartness for expanded cooperation. The article contributes to the fast-changing smart home industry by capturing the attributes that define today’s SHAs, demonstrating that these attributes can contribute to the development of smart homes as a competitive PSS, and identifying areas of focus for those who develop SHAs and systems.

To improve data reliability in NoC, extensively adopted method is the deployment of error correction codes. Errors present in the data flit are corrected by these codes and this is not applicable for correcting errors present in the header flit. So, there is a need for an coding method which will correct errors in data and also the header flit. Further, it is important to have a coding method that will decode the header flit faster compared to data flit, as header flit is used for processing the data flits. Existing single error correction and double error detection code is improved and presented in this paper to support faster error correction in header flit with retaining the same number of redundant bits. This improved code is synthesised and results are compared with existing code. The results show that the header flit are decoded faster compared to data flits as the critical path delay is reduced.

This paper presents the reliability improvement of self-adjusting output data compression technique. Our theoretical investigation showed that compression of both address and data allows to achieve single word error detection and correction, and double word error detection. Possible built-in self-test architecture is proposed.

Single bit errors occur more frequently in memory elements. So for the avoidance of these single bit errors the Hamming code technique was recognized as the best among all other coding techniques. The most effective coding technique was Hamming [16, 11, 5] <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> which results in single error detection and correction as well as double adjacent error detection and correction. In this paper, a method to design SEC-DAEC codes with optimized decoding is presented and evaluated. Extended Hamming code is developed by adding an extra parity bit. The implementation is evaluated and compared by its application in an audio signal authentication in matlab with introduced errors The evaluations show there is a slight increase in area, power and delay of the decoder.

Due to scaling in CMOS technology, multiple bit upsets (MBUs) have been widely occurred in memories. As a result, multiple adjacent bits of memories are corrupted and valuable information are lost forever. To mitigate these problems, multi-bit adjacent error-correcting codes are generally employed in SRAM memories. Single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are used to mitigate radiation or noise source induced MBUs to protect static random access memory (SRAM) devices. These codes are able to correct single and double adjacent errors, and also detect double errors. In this paper, three different SEC-DED-DAEC codes have been designed and implemented for SRAM memories. All functional blocks of these codecs are simulated and synthesized both in FPGA and ASIC platforms. Performances of the different SEC-DED-DAEC codes are observed in terms of area and delay.

Error control coding improves reliability and efficiency of wireless communication systems. This research delves into the latest advancements in error control coding schemes for wireless communication systems, with a specific focus on their application within the domain of Low Power Wide Area Networks (LPWANs) such as Narrowband Internet of Things (NB-IoT) systems, LoRa energy-efficient hardware design, random access control systems, and wireless sensor networks. In the context of LPWANs, particularly NB-IoT systems, we investigate the adaptive coding and modulation (ACM) in NB-IoT systems, which adapts coding rates and modulation techniques to changing channel circumstances. Comprehensive analysis of the literature review shows that the proposed approaches are more energy efficient and less error-prone than fixed coding and modulation schemes. Using Cell Design Methodology (CDM), Single Error Correction (SEC) codes are optimized for energy efficiency. Power and energy efficiency have improved in standard CMOS and CDM logic systems. This impacts IoT devices, memory storage, and security systems. Next, Forward Error Correction (FEC) is examined for ALOHA-based random-access control systems wherein packet loss rate and spectral efficiency metrics are mathematically calculated. FEC is beneficial, especially when time and frequency synchronization diverge. Monte Carlo simulations studied in the literature shows that FEC improves satellite communication systems. This review establishes benefits of FEC, notably in satellite communications systems. In addition, Wireless Sensor Networks (WSNs) error control techniques and network reliability and performance are examined along with Convolutional, Turbo, Low density parity check codes(LDPC), and Polar error correction coding (ECC) methods. We learn about their benefits, drawbacks, and implementation challenges by assessing their efficacy, efficiency, and applicability in wireless sensor networks (WSN) applications. This study further highlights advancements of energy-efficient error control coding when, integrated into network designs alongwith the trade-offs between efficacy and intricacy to help improve wireless communication networks. Finally, this study summarizes current error control coding approaches for wireless communication systems. We provide insights into improving reliability, energy conservation, and efficacy by examining ACM, CDM, FEC, and error correction coding (ECC) across varied domains including LPWAN and IoT technologies with earnest hope to facilitate researchers, engineers, and professionals working in the field of error control coding in wireless communication.

The electric mobility dissemination is forcing the adoption of new technologies and operation paradigms, not only focusing on smart grids, but also on smart homes. In fact, the emerging technologies for smart homes are also altering the conventional grids toward smart grids. By combining the key pillars of electric mobility and smart homes, this paper characterizes the paradigms of the electric vehicle (EV) in smart homes, presenting a review about the state-of-the-art and establishing a relation with future perspectives. Since the smart home must be prepared to deal with the necessities of the EV, the analysis of both on-board and off-board battery charging systems are considered in the paper. Moreover, the inclusion of renewable energy sources, energy storage systems, and dc electrical appliances in smart homes towards sustainability is also considered in this paper, but framed in the perspective of an EV off-board battery charging system. As a pertinent contribution, this paper offers future perspectives for the EV in smart homes, including the possibility of ac, dc, and hybrid smart homes. Covering all of these aspects, exemplificative and key results are presented based on numerical simulations and experimental results obtained with a proof-of-concept prototype.

Circuit techniques for reducing the minimum supply voltage (V MIN ) of last-level and intermediate static random-access memory (SRAM) caches enhance processor energy efficiency. For the first time at a 16nm technology node, projections of a high-density 6-transistor SRAM bit cell indicate that the VMIN of a 4Mb or larger cache exceeds the maximum supply voltage (V MAX ) for reliability. Thus, circuit techniques for cache VMIN reduction are transitioning from an energy-efficient solution to a requirement for cache functionality. Traditionally, error-correcting codes (ECC) such as single-error correction, double-error detection (SECDED) aim to protect the cache operation from radiation-induced soft errors. Moreover, during the qualification of a system-on-chip (SoC) processor, test engineers monitor the rate of correctable cache errors from SECDED for observing the on-die interactions between integrated components (e.g., CPU, GPU, DSP, etc.). This presentation highlights the opportunity to exploit ECC for reducing the cache V MIN while simultaneously providing coverage for radiation-induced soft errors. Silicon test-chip measurements from a 7Mb data cache in a 20nm technology demonstrate a V MIN reduction of 19% from SECDED. In addition, silicon measurements provide a salient insight in that only 0.12% of the cache words contain an error when operating at the cache V MIN with SECDED. Therefore, SECDED improves V MIN by 19% while maintaining 99.88% coverage for radiation-induced soft errors. In applying SECDED for a lower cache VMIN, the rate of correctable errors exponentially increases, thus eliminating a useful metric for on-die observability. The presentation concludes by offering alternative solutions for on-die observability.

In recent years, many internet of things (IoT) platforms based on cloud computing have been proposed for general purpose applications. Though many similar platforms or schemes particular for smart home applications have been proposed, many issues such as multiple connectivity due to diversity of smart home applications and supporting for real-time operations have not been solved properly. We propose a smart home foundation scheme adopting open source hardware devices and cloud computing technology to explore these issues. In this scheme, Arduino Yun-based smart hardware devices can connect to the cloud server through multiple network connectivity. By utilising Spacebrew technology, a bidirectional real-time communication can be implemented which provides a solid foundation for real-time operations of smart home. The core functions of the scheme are exposed through RESTful web services in a SaaS (short for software as a service) manner and can be called by various clients and other applications. Demonstrative applications show that the proposed smart home foundation scheme provides adequate support for creating smart home applications based on wireless open source hardware devices.