<title>Spatial and color clustering on an FPGA-based computer system</title>

Field Programmable Gate Array Reliability Analysis Using the Dynamic Flowgraph Methodology

The 21st century has brought digitization ofknowledge, but as libraries go digital, inclusive search tools arebecoming necessary. Though most digital searches cater to highresourcelanguages, leaving speakers of low-resource languages,like Uzbek, underserved. This research proposes an originalconcept for semantic searches in digital libraries tailoredaround the language, culture, and socio-technical milieu of lowresourcelanguages like Karapalpak, Tajik, and regionaldialects of Uzbek. Our solution integrates numeroussophisticated systems to overcome key challenges like the lackof annotated corpora, embarrassment of morphologicalcomplexity, multilingualism, and others. We design acomprehensive semantic search engine that provides meaningawaresearch results aligned with users' intent, regardless of thelinguistic variations and custom-built domain-specific languageresources, multilingual embeddings, and ontologies used. Theframework enables semi-automatic transliteration, crosslanguageretrieval, context-driven query expansion, and out-oflanguagequery imposition. The system, implemented as aprototype on a Uzbekistan digital library corpus,demonstratively surpasses keyword-based searches in accuracyand user satisfaction. This research will promote thedevelopment of knowledge systems that are more culturallyaligned and relevant to users, applicable to other languages withfew accessible resources.

In this paper an implementation of the Inverse Numerical Laplace Transform (INLT) on a Field Programmable Gate Array (FPGA) is presented. A brief description of INLT algorithms based on FFT are made and its MATLAB implementation is performed in order to have a comparison basis with FPGA results. A fixed point representation is used and it is optimized using fi MATLAB object. INLT is basically composed by three stages: Windowing, FFT and exponential function multiplications, the last stage is considered the critical one because it can result in severely large errors, specially, when several samples are required. Errors can be reduced by increasing the number of bits, however this increment makes the required FPGA area greater. Windowing and FFT can be implemented with high accuracy on FPGA with CORDIC and Cooley Tukey algorithms respectively, making the implementation flexible. The implementation was made with Verilog description hardware language using Xilinx technology and Virtex 6 FPGA.

A fast burst error-correction decoder is proposed. It can be used for high-speed decoding of a burst error-correcting Fire code having the generator polynomial G(x) = (1 + x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sup> )p(x), where p(x) is irreducible and of degree m and the degree of G (x) is r = c + m, r being the number of redundancy bits. The decoder needs at most r -1 cycles to find both the error burst pattern and its location, whereas conventional decoding needs up to n cycles [1] (n is the number of bits in a codeword), or a fraction of n [2]. The decoding scheme is based on new aspects of the structure of the error syndrome and the parity check matrix of Fire code recently observed by the author. These aspects allow partial syndrome processing in the decoding process. This makes hardware costs relatively low and enables very high-speed decoding. The decoding scheme makes use of modern mapping devices such as programmable read only memories (PROM's) and field programmable logic arrays (FPLA's), resulting in relatively compact and cheap hardware. The encoder/decoder could probably be implemented as a single-chip LSI circuit.

With the advancements in utilizing Artificial Intelligence (AI) in embedded safety-critical systems based on Field-Programmable Gate Arrays (FPGAs), assuring that these systems meet their safety requirements is of paramount importance for their revenue service. Based on this context, this paper has two main objectives. The first of them is to present the Safety ArtISt method, developed by the authors to guide the lifecycle of AI-based safety-critical systems, and emphasize its FPGA-oriented tasks and recommended practice towards safety assurance. The second one is to illustrate the application of Safety ArtISt with an FPGA-based braking control system for autonomous vehicles relying on explainable AI generated with High-Level Synthesis. The results indicate that Safety ArtISt played four main roles in the safety lifecycle of AI-based systems for FPGAs. Firstly, it provided guidance in identifying the safety-critical role of activities such as sensitivity analyses for numeric representation and FPGA dimensioning to achieve safety. Furthermore, it allowed building qualitative and quantitative safety arguments from analyses and physical experimentation with actual FPGAs. It also allowed the early detection of safety issues—thus reducing project costs—and, ultimately, it uncovered relevant challenges not discussed in detail when designing safety-critical, explainable AI for FPGAs.

This paper describes the proposed implementation of accelerometer measurement on the FPGA platform. The FPGA platform is used to utilise the parallelism features offer by the FPGA instead of other processing devices. The acceleration measurement is designed using G-code in LabVIEW FPGA and then implemented on the NI sbRIO-9632 FPGA board using VHDL. The implementation results are evaluated in terms of FPGA speed and usage of FPGA resources. It shows that the acceleration measurement on the FPGA board utilises approximately 15% of FPGA resources with approximately 44MHz FPGA speed. The execution time of the acceleration measurement module shows the FPGA-based implementation outperforms the microcontroller-based implementation. The correctness of the computed output by the FPGA board is also verified. These findings provide insight into the implementation of real-time monitoring applications, particularly for the human motion measurement system on the FPGA platform.

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.

A data acquisition system for a single-ring, high-resolution, small-animal PET scanner is described. This single-ring test system is part of the development of a multiring scanner. The system was designed to be as simple (short development cycle, and low cost) and as flexible as possible while maintaining high performance standards necessary for high-resolution quantitative studies. Unlike the multiring system electronics under development, the test system does not use a clock, but identifies coincidences by overlapping logic signals. The ring consists of up to 18 multicrystal MiCE modules, each of which is coupled to a resistive summing board that produces two X and two Y position signals. These are sent to the inputs of an analog multiplexer circuit. Total energy signals are also produced and used as inputs to NIM discriminators. A field programmable gate array (FPGA) is used for all system logic functions. This allows software development, testing, implementation, and modification of logic circuitry without hardware modification. Inputs to the FPGA are the outputs of the 18 discriminators. The FPGA logic produces and locks an event signal whenever two modules along allowed lines of response trigger within a preset resolving time. The FPGA also produces detector codes identifying the detectors involved in the event. These are recorded and also sent to the multiplexer to switch the position signals from the modules involved in the event to a buffered CAMAC ADC system for digitization. A "not busy" signal from the ADC is used to reset the FPGA releasing the locked signals allowing further event acquisition.

Field programmable gate arrays (FPGAs) have drawn wide attention from nuclear power industry for digital instrument and control applications (DI&amp;C), because it’s much easier and simpler than microprocessor-based applications, which makes it more reliable. FPGAs can also enhance safety margins of the plant with potential possibility for power upgrading at normal operation. For these reasons, more and more nuclear power corporations and research institutes are treating FPGA-based protection system as a technical alternative. As nuclear power industry requires high reliability and safety for DI&amp;C Systems, the development method and process should be fully verified and validated. For this reason, to improve the application of FPGA in NPP I&amp;C system, the specific test methods are critical for the developers and regulators. However, current international standards and research reports, like IEC 62566 and NUREG/CR-7006, which have demonstrated the life circle of the development of FPGA-based safety critical DI&amp;C in NPPs, but the specific test requirements and methods which are significant to the developers are not provided. In this paper, the whole test process of a pressurized water reactor (PWR) protection sub-system (Primary Coolant Flow Low Protection, Over Temperature Delta T Protection, Over Power Delta T Protection) is described, including detail component and integration tests. The Universal Verification Methodology (UVM) based on System Verilog class libraries is applied to establish the verification test platform. All these tests are conducted in a simulation environment. The test process is driven by the test coverage which includes code coverages (i.e., Statement, Branch, Condition and Expression, Toggle, Finite State Machine) and function coverage. Specifically, Register Transaction Level (RTL) simulation is conducted for Component tests, while RTL simulation, Gate Level simulation, Timing simulation and Static timing analysis are conducted for the integration test. The issues (e.g., the floating point calculation, FPGA resource allocation and optimization) arose in the test process are also analyzed and discussed, which can be references for the developers in this area. The component and integration tests are part of the Verification and Validation (V&amp;V) work, which should be done by the V&amp;V team separated from the development team. The testing method could assure the test results reliable and authentic. It is practical and useful for the development and V&amp;V of FPGA-based safety DI&amp;C systems.

This paper presents a field-programmable gate array (FPGA)-based emulator for rapidly prototyping a non-volatile (NV)-FPGA-based system on chip (SoC) where an FPGA, a central processing unit, and other peripheral modules are integrated into a single chip to address the difficulty in estimating the usefulness of an NV-FPGA-based SoC on a target system. By mimicking the NV-memory device as a sequential logic circuit, a virtual NV-FPGA SoC is implemented on a commercial FPGA board, and its system-level functional verification is performed. As a typical design example, the proposed hardware is implemented on a Digilent Basys 3 board. A fundamental arithmetic logic circuit is implemented on the NV-FPGA, and its logical behavior is the same as that of the original circuit, and NV-logic-specific functions, i.e. store and recall operations are successfully confirmed. Additionally, a 96.3% power reduction is estimated by the NV-FPGA SoC compared to that of a volatile FPGA SoC system under 1.83% of activity ratio.

ABSTRACTWhen a serendipitous discovery is made while searching within a digital library collection (such as an academic digital library at a university), the searcher has a difficult choice to make: either pursue the serendipitous discovery or set it aside and deal with it later. If they take the first option, this breaks the flow of the primary search activity which may make it difficult to resume. If they take the second option, they may have difficulty re‐finding what they discovered when they are finished with the primary search activity. We have developed a novel search interface that includes topic‐based workspaces and a “read it later” list. Serendipitous discoveries can be easily added to the “read it later” list, allowing the searcher to stay focused on their current search activity knowing that they can easily return to the discovered resource. For each resource saved to the “read it later” list, a textual similarity is calculated against the collection of documents saved in each of the searcher's workspaces. This allows them to easily identify which of their prior search tasks is a best fit for the discovery, as well as an ability to create a new workspace if desired.

Particle1 Filter (PF) is an effective algorithm often used in tracking systems. But the complexity of PF algorithm leads to a large amount of computation and operation time, especially in embedded systems. Field Programmable Gate Arrays (FPGA) parallelism can accelerate the algorithm to make the tracking real-time. Traditional PF algorithm decreases the error of the target location or increases the tracking accuracy by increasing the number of particles. It will consume much memory resources of FPGA or external storage chips. We propose a hardware architecture of improved PF algorithm in this paper which modifies the centroid of the random particles using Camshift algorithm. A decision mechanism of tracking and lost status is presented during the real-time tracking. Experiments on ALTERA DE2-115 board show that the improved PF algorithm increases the tracking accuracy, reduces FPGA memory resources, and ensures real-time performance.

Recent research has shown that field programmable gate arrays (FPGAs) have a large potential for accelerating demanding applications, such as high performance digital signal process applications with low-volume market. The loss of generality in the architecture is one disadvantage of using FPGAs, however, the reconfigurability of FPGAs allow reprogramming for other applications. Therefore, a uniform FPGA-based architecture, an efficient programming model, and a simple mapping method are paramount for the wide acceptance of FPGA technology. This paper presents MASALA, a dynamically reconfigurable FPGA-based accelerator for parallel programs written in thread-intensive and explicit memory management (TEMM) programming models. Our system uses a TEMM programming model to parallelize demanding applications, including application decomposition into separate thread blocks and compute and data load/store decoupling. Hardware engines are included into MASALA using partial dynamic reconfiguration modules, each of which encapsulates a thread process engine that implements the hardware's thread functionality. A data dispatching scheme is also included in MASALA to enable the explicit communication of multiple memory hierarchies such as interhardware engines, host processors, and hardware engines. Finally, this paper illustrates a multi-FPGA prototype system of the presented architecture: MASALA-SX. A large synthetic aperture radar image formatting experiment shows that MASALA's architecture facilitates the construction of a TEMM program accelerator by providing greater performance and less power consumption than current CPU platforms, without sacrificing programmability, flexibility, and scalability.

In this paper a switching control scheme of ZVS Bidirectional DC to DC converter using Field Programmable Gate Array (FPGA) is presented. The aim of this work was to reduce the Electromagnetic interference using FPGA. A software program using the Hardware Description Language, VHDL is developed for the generation of driving pulses to MOSFET Switches. Simulation and implementation results of control architecture are obtained using Modelsim and Xilinx software. Operation of the converter in boost mode and buck mode are verified using Matlab Simulink. FPGA-based system is proposed for the control of bidirectional DC to DC converter system. A dual half-bridge Bidirectional DC to DC converter is implemented using the generated driving pulses. Simulation and Experimental results of the converter system are presented.

Currently, in few countries, there have been many projects related to the development of Field Programmable Gate Array (FPGA)-based Instrumentation and control (I&C) system designs for their nuclear power plant (NPP), whether for modernization or the new development of NPPs. Indonesia already develops a study related to High Temperature Gas Cooled Reactor as the generation IV for NPPs type for these few years with a specific type which is High Temperature Reactor–10 MW (HTR-10). Since the FPGA-based technology is new in the field, and both the international standards and guidance, from national and international has not defined provisions this issue, therefore verification and validation (V&V) activities for this HTR-10 are mandatory to be included in the design life cycle of I&C system development to get license approval from the national regulatory body. The FPGA-based system needs concentration both in hardware and software development, but commonly only software-related standards that usually included in the design and V&V in the previous computer-based I&C system. Therefore, in this study the V&V plan needs to be developed to state the methods to be required regarding the correctness of the applications of FPGA based I&C system. By arranging this V&V method, we will see whether they are easily applicable to actual systems, had the result to reach the requirement to have reliability, availability, maintainability and safety aspects, and has shortened and easier V&V step than computer-based I&C system. From the results of this study, it can be seen that the results of the method used for V&V between Programmable Logic Controller (PLC)-based and FPGA are almost the same because both have almost the same requirements, especially in software design. Some testing is not mandatory for FPGA-based because of the reduced system complexity. The use of FPGA can shorten the V&V process which can also reduce costs.