Mask CD uniformity impact during incoming quality control

Critical Dimension (CD) Uniformity is one of the necessary parameters to assure good performance and reliable functionality of any integrated circuit (IC), and towards the advanced technology node 28nm and beyond, corresponding CD Uniformity becomes more and more crucial. It is found that bad mask CD Uniformity is a significant error source at 28nm process. The CD Uniformity on mask, if not controlled well, will badly impact wafer CD performance, and it has been well-studied that CD Uniformity issue from gate line-width in transistors would affect the device performance directly. In this paper we present a novel solution for mask global CD uniformity error correction, which is called as global loading effect correction (GLEC) method and applied nesting in the mask exposure map during the electron beam exposure. There are factors such as global chip layout, writing sequence and chip pattern density distribution (Global Loading), that work on the whole mask CD Uniformity, especially Global Loading is the key factor related to mask global CD error. From our experimental results, different pattern density distribution on mask significantly influenced the final mask CD Uniformity: the mask with undulating pattern density distribution provides much worse CD Uniformity than that with uniform one. Therefore, a GLEC model based on pattern density has been created to compensate the global error during the electron beam exposure, which has been proved to be efficacious to improve mask global CD Uniformity performance. Furthermore, it ’s also revealed that pattern type is another important impact factor, and GLEC coefficient need be modified due to the specific pattern type (e.g. dense line-space only, iso-space only or an average of them) to improve the corresponding mask CD uniformity.

Extreme ultraviolet lithography (EUVL) is getting closer to practical use for mass production every year. For applying EUV lithography to manufacturing, productivity improvement is a critical challenge. Throughput and yield are important factors for productivity. EUV source power is steadily advancing year by year, bringing improvements in throughput. Furthermore, yield improvement is necessary for productivity enhancement. In order to improve the yield in EUV lithography processing, further improvement of defectivity and critical dimension (CD) uniformity is required. Reduction of residue and in-film particle defects is very crucial work to enhance the productivity. For residue defects, it is found that the residue defects detected after development inspection (ADI) are perfectly transferred to after etching inspection (AEI), meaning that high defectivity of residue deteriorates yield directly. Furthermore, in-film particle defect counts increase from ADI to AEI because particles included in spin-on-carbon (SOC) and spin-on-glass (SOG) as well as that in resist film are the sources of defects in AEI, while particles mainly included in resist film can be observed in ADI. Figure 1 shows the normalized defectivity comparison between conventional rinse and filtration used and optimizing rinse used and improving filtration efficiency in ADI and AEI. ADI defectivity in which optimized rinse is applied and improving filtration efficiency achieved 0.04, while that in which conventional rinse and filtration are used defined 1.00, meaning the 96 % of improvement. In addition, AEI defectivity by using optimized rinse and improving of filtration efficiency shows 86 % of reduction as compared with that using conventional rinse and filtration. These results reveal that our novel actions for rinse and material supply show excellent performance for defect reduction. For the other aspect of yield improvement, CD uniformity control is one of the crucial factors. CD variations are comprised of several components such as wafer to wafer CD uniformity, field to field CD uniformity. To achieve CD uniformity target for manufacturing, we have optimized developing process with the latest technology. Then, 15 % of field to field CD uniformity improvement and significant improvement of wafer to wafer CD uniformity are achieved.

Critical dimension (CD) uniformity performance has improved significantly over the years by optimizing postbaking and development steps. As we continue to improve CD uniformity with PBS, our focus has shifted to other steps in the process. The crossover step, the point in the process where both develop and rinse are introduced simultaneously, has often been thought to have little or no effect on the develop time or to influence the uniformity results. However, careful examination of this step has determined that the crossover time, spin speed, and concentration of the develop/rinse mixture can have a significant effect on CD uniformity. Reduction of the typical radial effect was noted. Several design of experiment projects were run to examine these variables. A screening experiment was first run to determine the significant variables and their influence on uniformity. An optimization run was then made on crossover conditions, which included examination of plates from several vendors. Repeatability and sensitivity of the process to other variables were also determined. Results and recommendations are presented in this paper.

With the development of the lithography, the demand for critical dimension (CD) and CD uniformity (CDU) has reached a new level, which is harder and harder to achieve. There exists reflection at the interface between photo-resist and substrate during lithography exposure. This reflection has negative impact on CD and CDU control. It is possible to optimize the litho stack and film stack thickness on different lithography conditions. With the optimized stack, the total reflectivity for all incident angles at the interface can be controlled less than 0.5%, ideally 0.1%, which enhances process window (PW) most of the time. The theoretical results are verified by the experiment results from foundry, which helps the foundry achieve the mass production finally.

In this paper the bias table models for the wafer scale SmartNIL™ technology are addressed and validated using complete Scanning Electron Microscopy (SEM) characterizations and polynomial interpolation functions. Like the other nanoimprint lithography (NIL) technics, this replication technology is known to induce Critical Dimension (CD) variations between the master and the imprint, due to polymer shrinkage, soft stamp deformation or thermal expansion. The bias between the former and final object follows peculiar rules which are specific to this process. To emphasis these singularities, Critical Dimension (CD) uniformity analyses were analyzed onto 200 mm wafers imprinted with the HERCULES® NIL equipment platform. Dedicated masters were manufactured to capture the process signatures: horizontal and vertical line arrays, local densities ranging from 0.1 to 0.9 and minimum CD of 250 nm. The silicon masters were manufactured with 248 optical lithography and dry etching and treated with an anti-sticking layer from Arkema. CD measurements were made for the master and the replicates on 48 well selected features to build interpolations. The bias table, modelled by polynomial functions with a degree of 5 for the density and a degree of 3 for the CD, are compared between horizontal and vertical features, and between the center and the edge of the wafers. Finally the focus is made on the validation of the interpolations by comparing the computed bias and the experimental data.

In recent years, mask critical dimension (CD) linearity and uniformity has become increasingly important. The ITRS roadmap shows the mask CD control requirements exceeding those of the wafer side beyond the 45nm node. Measurements show that there are systematic, uncorrected proximity effects even when a state-of-the-art proximity effect correction (PEC) algorithm is used. The uncorrected proximity effect is predictable with a computational model. The model for e-beam lithography and etch process contains terms to model short-range pattern density effects and plasma shadowing effect in Cr-etch. The model is calibrated using CD measurements on a test mask. The model is valid for arbitrary 2-D patterns. We present a model-based mask process compensation (MPC) method which applies geometric changes to polygons as in OPC. We discuss the goodness of model fit to the calibration data; verification of the calibrated model by SEM images; and the improvement obtained by MPC. The mask writing error, i.e. final inspection CD minus incoming database CD, was reduced by a factor of 2 through the use of MPC.

As optical lithography will be extended to device generations below 150 nm of design rule, the critical dimension (CD) uniformity on a photomask is required to be as small as 13 nm (3(sigma) ). The relationship between development method and dark erosion is discussed in view of CD variations. The temperature variation on a photomask is found to be more than 4 degrees Celsius for a conventional spin-spray development. An optimized process using a 'puddle process' to minimize developer temperature effect and non-uniform spray pressure effect on CD variation. The CD uniformity using the optimized process brings 11 nm in 3(sigma) over 127 mm X 127 mm area on a 6-inch mask.

Reticle critical dimension uniformity (CDU) is an important criterion for the qualification of mask layer processes. Normally, the smaller the three sigma value of reticle CDU is, the better is the reticle CDU performance. For qualification of mask processes, the mask layers to be qualified should have a comparable reticle CDU compared to the process of record (POR) mask layers. Because the reticle critical dimension (CD) measurement is based on algorithms like “middle side lobe measurement”, evaluation of the reticle CD-values can not reflect aspects like the sidewall angle of the reticle and variation in corner rounding which may be critical for 45nm technology nodes (and below). All involved tools and processes contribute to the wafer intra-field CDU (scanner, track, reticle, metrology). Normally, the reticle contribution to the wafer CDU should be as small as possible. In order to reduce the process contributions to the wafer intra-field CDU during the mask qualification process, the same toolset (exposure tool, metrology tool) should be applied as for the POR. Out of the results of these investigations the correlation between wafer measurement to target (MTT) and reticle MTT can be obtained in order to accurately qualify the CDU performance of the mask processes. We will demonstrate the correlation between reticle MTT and wafer MTT by use of multiple mask processes and alternative mask blank materials. We will investigate the results of four process-layers looking at advanced binary maskblank material from two different suppliers (moreover the results of a 2X-via layer as an example for a phase-shift maskblank is discussed). Objective of this article is to demonstrate the distribution between reticle MTT and wafer MTT as a qualification criterion for mask processes. The correlation between wafer CD-difference and reticle CD-difference of these mask processes are demonstrated by having performed investigations of dense features of different 28nmtechnology process layers (poly-, active-, contact-, 1X-metal-, 2X-via layers). Referring to the correlation between wafer and reticle MTT, the contribution of the reticle CD-difference to the wafer CD-difference can be used as an evaluation method for the transfer-process of different mask sites.

As pattern design rule of device shrinks, CD control becomes more critical and important especially for resistance devices. As CD (Critical Dimension) increases, CDU (Critical Dimension Uniformity) becomes worse generally. The question with this relationship is a starting point of our study. Mainly we focused on two points. One is which factor affects CDU. The other is whether CDU degradation with large CD happens at all cases or not. We have analyzed with simulation and experiment results about CDU with splitted mask layout CD under limited conditions such as same equipment, illumination and exposure dose. As a result, we will show the relationship between CD size and CDU.

As the essential techniques for the CD (Critical Dimension) measurement of the LCD pattern, there are various modules such as an optics design, auto-focus [1-4], and precise edge detection. Since the operation of image enhancement to improve the CD measurement repeatability, a ring type of the reflected lighting optics is devised. It has a simpler structure than the transmission light optics, but it delivers the same output. The edge detection is the most essential function of the CD measurements. The CD measurement is a vital inspection for LCDs [5-6] and semiconductors [7-8] to improve the production yield rate, there are numbers of techniques to measure the CD. So in this study, a new subpixel algorithm is developed through facet modeling, which complements the previous sub-pixel edge detection algorithm. Currently this CD measurement system is being used in LCD manufacturing systems for repeatability of less than 30 nm.

Traditionally, lithography critical dimension (CD) measurements with stepper de-focus and deltas in sidewall angle do not correlate well with the ultimate product measurement, namely electrical performance. It is important in etch bias control, therefore, to control more than just the physical CD. It is at a minimum, important to show how the changes in sidewall angle control at lithography relate to etch biases. This is especially important as chip geometries shrink, and the size and shape of the sidewall becomes a larger portion of the line width geometry. This makes precise CD measurements coupled with slope angle measurements, in real time, important to process control in lithography so that ultimately the desired dimension is achieved at the post etch step, and therefore electrical performance can be gauged. We will present data taken from Focus/Exposure Matrices in the form of CD measurements, in-line sidewall angle reconstruction, and electrical measurements. We hope to correlate electrical performance to post develop CD and slope sidewall angle as measured without destructive cross sections.

In advanced CMOS technology node, the dummy gate critical dimension (CD) and its line head to head (HTH) space CD will directly affect the device performance and its long term reliability. Macro- and micro-uniformity of dummy gate CD and its HTH CD are key parameters for wafer yield and product quality. In dummy gate process, both the thickness uniformity of film stack (silicon nitride, amorphous carbon and etc.) and the CD uniformity (CDU) of lithography line will influence final dummy gate CDU. Feed forward APC mode for dummy gate CDU improvement requests a long term work in semiconductor manufacturing which is not a focus point here. In this paper, an advanced temperature compensation function of a commercial inductively coupled plasma (ICP) etcher will be mentioned. At the same time, both dummy gate and HTH CDU tuning by this function with feedback mode will be introduced. Some possible enhanced solutions of CDU improvement will also be addressed in this paper.

Introduction and problem statement Given that EUV lithography allows printing smaller Critical Dimension (CD) features, it can result in non-normal distributed CD populations on ADI wafers [Civay SPIE AL 2014], leading to errors in predicted failure rates [Bristol SPIE AL 2017]. As a result, there is a need to quantify the actual behavior of the CD population extremes by means of massive metrology [Dillen EUVL 2018]. Not only allows this to study the CD distribution, we can in parallel also evaluate pattern quality and the failure mechanisms leading to defects. This massive metrology method provides an accurate failure rate based on CD, and enables new possibilities to define a failure rate based on different metrics in a single measurement. Method We analyze the CD uniformity of pillars in polar coordinates using a global waveform based thresholding strategy. In conjunction with this CD information, we also evaluated the print quality of each individual measured feature. Fig 1. In line detected anomalies and failure definitions As we gather this information during the measurement of CD, we can limit the additional measurement overhead to neglectable levels. Application and outlook We will show how we can leverage this to determine a defect based process window and relations of failure mechanisms through process conditions (see figure 2). When we take failures in a CH dataset into account, we illustrate the effect on the shape of a large dataset distribution in figure 3. Fig 2. Defect identification for a through exposure dose experiment of pillars. For each condition >13k pillars where measured. The plot clearly shows an asymmetric behavior due to different failure mechanisms at low and high energy. The 2 vertical lines at relative energies 0.93 and 1.05 times nominal indicate the low defect process window. Fig 3. A distribution of measured regular grid dense CH. The red line is the unfiltered CD data, the blue line is the shape of the distribution after filtering individual CH measurements that have a much lower contrast than expected.

The dispositioning of mask defects must also heed the increasing gap between the lithography wavelength and wafer-feature widths. For the larger technology nodes, where printed-wafer shapes are similar to those on the mask, mask-level analysis is sufficient. However, for smaller nodes, wafer-level scoring is useful since every defect does not significantly impact the wafer. Wafer-level analysis often relies on measurements of critical dimension (CD). However, as reticle enhancement technology proliferates, there are increasingly more curved edges where CD cannot be used. For example, false alarms can result from measuring CD near line ends because slight variations in measurement position may produce large CD changes. More importantly, a killer defect may be missed if cutlines are forbidden near line ends because the CD measurements are too far from the defect. Wherever CD measurements are not advisable, we advocate the use of Area scoring by computing the difference in printed feature area. We are not abandoning CD scoring but rather combining it with Area scoring, and using the more pessimistic score. For Area scoring, we use (Defect area - Reference area)/(Reference area). In general, the reference area is difficult to define since many shapes are not easily parsed into primitive shapes. Therefore, we use a square of side equal to the target CD. This square defines the window for a sliding-window average of the area difference. The maximum average value is then chosen from the entire image. Unlike Edge Placement Error, Area is sensitive to long, thin difference regions. Unlike Flux or Maximum Intensity Difference, Area is threshold-aware; it measures what prints and shows process-window variation.

The Hitachi Model S-6280 high resolution field emission Scanning Electron Microscope (SEM) is used at Motorola's MOS-12 facility for Critical Dimension (CD) measurements of less than 1 micrometer in size. This tool is used to measure 200-mm diameter wafers with a low accelerating voltage in the range 0.7-1.0 kV. During new process development the tool is run in both manual mode and in a fully automated mode utilizing patten recognition for global alignment as well as feature CD measurement. Results on the reproducibility of fully- automated measurements show that this technique provides a significantly improved measurement capability compared to the standard manual technique.