Merging C and assembly language in microcontroller applications

Microprogramming has traditionally been done in assembly language because of the perceived need for fast execution; compiler technology does not yet exist for discovering and performing many of the clever tricks of an experienced microprogrammer. Unfortunately, programming at the machine-instruction level is both tedious and error-prone. A possible compromise between these two approaches is that of an interactive compiler, where the programmer guides the crafting of critical data structures and sections of code, while the compiler ensures that the resulting code has the same semantics as the original program, generates code where speed is not critical, and performs bookkeeping tasks. We are in the process of implementing a prototype of such a system. This paper describes the system being developed and discusses some of the key design issues.

Microprogramming has traditionally been done in assembly language because of the perceived need for fast execution; compiler technology does not yet exist for discovering and performing many of the clever tricks of an experienced microprogrammer. Unfortunately, programming at the machine-instruction level is both tedious and error-prone. A possible compromise between these two approaches is that of an interactive compiler, where the programmer guides the crafting of critical data structures and sections of code, while the compiler ensures that the resulting code has the same semantics as the original program, generates code where speed is not critical, and performs bookkeeping tasks. We are in the process of implementing a prototype of such a system. This paper describes the system being developed and discusses some of the key design issues.

In the world of supercomputers, the goal is higher and higher performance. To obtain the highest performance on a particular computational kernel, it is usually necessary to write assembly language. Compiler technology has not matured to the point of being able to take advantage many of the features of the i860 automatically. To approach the peak performance of the chip, it is currently necessary to use custom assembly language code. It is important to know which combinations of assembly instructions offer the highest performance, and which combinations cannot run at full speed. This paper assumes that you are already acquainted with the basics of the i860 microprocessor assembly language, and concentrates on describing how to enhance the performance of your code using 860 assembly language.

Extracting performance from many-core architectures requires software engineers to create multi-threaded applications, which significantly complicates the already daunting task of software development. One solution to this problem is automatic compile-time parallelization, which can ease the burden on software developers in many situations. Clearly, automatic parallelization in its present form is not suitable for many application domains and new compiler analyses are needed address its shortcomings.

10 - Hardware and software development tools

Faced with ever-increasing constraints of budget reductions and fight schedules, test engineers are looking for faster, more cost-efficient ways to get automatic test equipment (ATE) systems up and running. This case study examines a process known as Freedom/sup TM/ Series, developed by Racal Instruments, illustrating how the principles of design reuse and automation, applied to ATE systems, can dramatically reduce non-recurring engineering costs and accelerate schedules. Freedom Series is a modular approach to ATE system design. It exploits design reuse by standardizing components such as test instruments, interface cables, software drivers, and documentation. In addition, Freedom Series provides software tools that automate many non-recurring engineering tasks. The combination of modularity, reuse, and automation accelerates the system integration process and, in many cases, virtually eliminates non-recurring engineering costs.

This article describes a commercial digital audio signal processor, the Eventide SP2016 (Fig. 1), together with a software development system that makes it possible for users to create their own realtime signal processing programs. The SP2016 is a general-purpose signal processor that is optimized for time-domain applications. It features two separate 16-bit analog-to-digital and digital-to-analog (ADC and DAC) channels to enable complete stereo operation at a full signal bandwidth of 16 KHz. As a stand-alone unit designed for professional recording studios, sound reinforcement, and electronic music applications, it does not require an external computer controller. All features can be operated from the front panel of the unit or from a hand-held remote control. Factory programs stored in erasable, programmable read-only memory (EPROM) are provided with the unit to perform many types of as well as delay, flanging, chorusing, filtering, loop editing, and other special effects. We discuss the architecture of the SP2016 and particularly its high-speed array processor and then describe the arithmetic-logic unit (ALU) assembly language and SPUD high-level language used to write SP2016 signal processing programs. We include as a programming example a simple reverberator with RT60 control. (RT60 refers to the it takes for to be 60 db down from its initial level. It is thus a way of saying reverberation time in a more precise way.) Finally, we describe the SPUDsystem development system, a portable software tool that can be used to create SP2016 programs. System Architecture

We developed a set of tools designed to provide rapid feedback to students as they learn to write programs in assembly language (LC-3, a RISC-like educational instruction set architecture). At the heart of the system is an extended version of KLEE, KLC3, that enables us to both identify issues and perform equivalence checking between student code and a gold (correct) version of each assignment. Feedback begins when students edit their code using a VSCode extension that leverages static analysis to perform a variety of correctness and style checks, encouraging students to improve their code quality. Each time a student commits code to their Git repository, our system triggers. Using KLC3 (KLEE), the student code is executed along with the gold version, and issues and behavioral differences are delivered back to the student through their Git repository as a human-readable report, test cases, and scripts. A queueing system allows students to monitor progress, but responses are generally available within minutes. We also extended the LC-3 simulation tools to support reverse debugging, making the process of finding complex bugs much more tractable for students, and used Emscripten to develop a browser-based interface for use in testing and debugging. Finally, our system maintains an individual regression test suite for each student and requires a submission to pass all previous tests before re-evaluation in KLC3, thus avoiding encouraging programming-by-guesswork. We deployed the system to provide feedback for the assembly programming assignments in a class of over 100 students in Fall 2020. Students wrote a median of around 700 lines of assembly for these assignments, making heavy use of our tools to understand and eliminate their bugs. Anonymous student feedback on the tools was uniformly positive. Since that semester, we have continued to refine and expand our tools' analysis capabilities and performance, and plan to deploy the system again in the near future (the class is offered every Fall).

A consensus appears to be developing in the programming community that every effort should be made to replace conventional programming techniques with structured programming in a language such as PL/I as soon as poseiole. This raises two questions: l) what can ce done by the programmer who must still pro;Tram in such unstructured languages as FORTRAN and Assembler Language, and 2) more important, how can students just learning to program oest be taught to write structured programs if only unstructured languages are available to them? In this paper, it is proposed that the programmer first write a structured version of his program in an informal algorithmic language (this can and should replace the conventional flowchart), then use the statements of the informal solution as comments in his actual program. Examples are given showing that the more unstructured the actual programming language, the more this simple technique can help in the development of structured programs and “structured programmers”.

: A tutorial description of NELIAC-N, the version of the NELIAC language implemented on the NAREC by means of the NELIAC-N compiler is presented. NELIAC is a problem-oriented, machine-independent programming language which enables programmers, scientists, and engineers to write their programs in a mathematical language rather than requiring an actual machine language or an assembly language. NELIAC thus minimizes the knowledge of the actual computer required by the programmer, maximizes the readability of the programs them selves, and provides carry-over valuue of pro grams from one computer to another.

The central processing unit (CPU) of a computer executes instructions encoded as a sequence of binary numbers. This program representation is commonly referred to as machine code. Assembly languages provide mnemonic abbreviations for the instructions of a computer. Program assemblers translate assembly language programs into machine code and binary data. Program assemblers allow the use of symbolic addresses (labels) to save the assembly language programmer from the tedious task of computing memory addresses manually. Macros provide textual substitution facilities. Pseudoinstructions, code optimizations, and just‐in‐time assembly complicate the task of program assemblers even more.

Nowadays, systems-on-chip have reached a level where nonrecurring engineering costs have become a great challenge due to the increase of design complexity and postfabrication errors. Embedded field programmable gate arrays (eFPGAs) represent a viable alternative to overcome these issues since they provide postmanufacturing flexibility that can reduce the number of chip redesigns and amortize chip fabrication cost. In this paper, we present an overview on eFPGAs and their architectures, computer aided design (CAD) tools, and design challenges. An eFPGA must be well-designed and accompanied by an optimized CAD tool suite to respond to target application's requirements in terms of power consumption, area, and performance. In this survey, we studied coarse-grained eFPGAs with customized blocks which are used for domain-specific applications and fine-grained eFPGAs that are used for general purposes but have lower performance.

Printed Electronics (PE) feature distinct and remarkable characteristics that make them a prominent technology for achieving true ubiquitous computing. This is particularly relevant in application domains that require conformal and ultra-low cost solutions, which have experienced limited penetration of computing until now. Unlike silicon-based technologies, PE offer unparalleled features such as non-recurring engineering costs, ultra-low manufacturing cost, and on-demand fabrication of conformal, flexible, non-toxic, and stretchable hardware. However, PE face certain limitations due to their large feature sizes, that impede the realization of complex circuits, such as machine learning classifiers. In this work, we address these limitations by leveraging the principles of Approximate Computing and Bespoke (fully-customized) design. We propose an automated framework for designing ultra-low power Multilayer Perceptron (MLP) classifiers which employs, for the first time, a holistic approach to approximate all functions of the MLP's neurons: multiplication, accumulation, and activation. Through comprehensive evaluation across various MLPs of varying size, our framework demonstrates the ability to enable battery-powered operation of even the most intricate MLP architecture examined, significantly surpassing the current state of the art.

Concerns about the availability and use of conventional nonrenewable energy sources have led to an increasing interest in renewable energy. Because renewable energy sources tend to be dilute and intermittent, solar power satellites have been proposed as a means of supplying large amounts of power continuously. Space solar power (SSP) will not be competitive for commercial-scale baseload power without some combination of greatly reduced launch and non-recurring engineering costs as well as space resource utilization. However, SSP may be competitive in the near term for niche markets where the fully burdened cost of delivery of conventional fuel is much higher than that for commercial markets. A model under development provides a tool to assess masses and costs of solar power satellites at a variety of power levels, orbits, and power transmission frequencies.

In the foreseeable future, VLSI design will meet a couple of explosions: explosion of power, explosion of integrity attackers including power integrity and signal integrity and explosion of NRE (non-recurring engineering cost). A remedy for power explosion and explosion of integrity attackers lies in ldquovoltage engineeringrdquo. A remedy for the NRE explosion is to reduce the number of developments and sell tens of millions of chips with a fixed design. 3D-stacked LSI approach may embody such possibility. The talk will cover example of the solutions based on 3D-stacking. Several new circuit technologies for voltage engineering, including distributed DC-DC converters and proximity interfaces are described to enable 3-D stacking of chips to build high-performance yet low-power electronics systems. On the other extreme of the silicon VLSIpsilas which stay as small as a centimeter square, a new domain of electronics called large-area integrated circuit as large as meters is waiting to open up a new continent of applications in the era of ubiquitous electronics. One of the implementations of the large-area electronics is based on organic transistors. The talk will provide perspectives of the organic circuit design taking E-skin, sheet-type scanner, Braille display and wireless power transmission and communication sheet as examples.