MF-ECC: Memory-Free Error Correction for Hyperdimensional Computing Edge Accelerators

The write operation asymmetry of many memory technologies causes different write failure rates at 0 →1 and 1 → 0 bit-flipping's. Conventional error correction codes (ECCs) spend the same efforts on both bit-flipping directions, leading to very unbalanced write reliability enchantment over different bit-flipping distributions of codewords (i.e., the number of 0 →1 or 1 → 0 bit-flipping's). In this work, we developed an analytic asymmetric write channel (AWC) model to analyze the asymmetric write errors in spin-transfer torque random access memory (STT-RAM) designs. A new ECC design concept, namely, content-dependent ECC (CD-ECC), is proposed to achieve balanced error correction at both bit-flipping directions. Two CD-ECC schemes - typical-corner-ECC (TCE) and worst-corner-ECC (WCE), are designed for the codewords with different bit-flipping distributions. Our simulation results show that compared to the common ECC schemes utilized in embedded applications like Hamming code, CD-ECCs can improve the STT-RAM write reliability by 10 - 30x with low hardware overhead and very marginal impact on system performance.

Increasing process variations coupled with aggressive scaling of cell area and operating voltage in the quest of higher density and lower power have greatly affected the reliability of on-chip memory. Error correction code (ECC) has been traditionally used inside memory to provide uniform protection to all bits in a code word. They suffer from either adequate protection against multibit failures or large overhead due to encoding/decoding logic and parity bits. To address this issue, we present a variable data-length ECC (VL-ECC) for the embedded memory devices of digital signal processors, in which the data length of ECC can be dynamically reconfigured to preferentially protect the relatively more important bits. In the proposed VL-ECC, when the number of failures exceeds the error correction capability, the data length of ECC is reduced to focus on the relatively more important higher order data bit parts, thereby minimizing system quality degradation due to bit failures. When the proposed VL-ECC is applied to the embedded memory devices of an H.264 processor, average peak signal-to-noise-ratio improvements of up to 5.12 dB are achieved compared with the conventional ECC under supply voltage of 800 mV or lower. With the fast Fourier transform processor, signal-to-quantization noise ratio is improved by up to 5.2 dB.

Due to the rapid technology scaling and increasing program/erase cycling, the raw bit error rate (RBER) in NAND flash memory keeps increasing rapidly. Conventional error correction codes (ECCs) with stronger protection capability are usually equipped for all flash pages as a solution to maintain the mandatory yield and reliability levels. However, the growth of RBER induced by increasing P/E cycles will lead to uneven distribution of errors. Applying uniform ECC protection capability for all flash pages might incur unnecessary hardware and latency overhead. Moreover, the overlong ECC check bits might be stored in two different flash pages. Therefore, two flash reads are required to retrieve a codeword. In this paper, ECC caching (E <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> C) techniques are proposed to cure these drawbacks of conventional uniform protection techniques. The main idea is to upgrade the ECC protection levels for flash pages when their correction slack is below the specified threshold. According to experimental results, we can enhance the reliability of flash memories significantly with negligible hardware cost.

Error-correcting codes (ECC) are widely used during data transfer in wireless communication systems as well as in computer memory architectures. The error-correcting process is based on sending data with extra parity bits and decoding the received data for error correction. The first error detection and correction code, introduced in 1950, Hamming Code (7,4) is a linear error-correcting code able to detect and correct a single-bit error by encoding 7-bit data from 4-bit data, including 3 parity bits. Previous efforts using unipolar resistive random access memory (ReRAM) based in-memory computation of Hamming Code (7,4) resulted in 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> times lower power consumption compared to GPU and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> times less than CPU-based computations. However further reduction of power consumption can be achieved by vector-matrix multiplication (VMM) using bipolar ReRAM arrays. In the VMM based approach, an encoding or decoding code matrix is stored in the array where it leverages the nonvolatile properties of ReRAM. With the VMM approach, the total number of computation cycles is not limited by the endurance of the ReRAM devices. Here we report the first experimental results of encoding and decoding Hamming code (7,4) using 1 transistor 1 hafnium oxide-based ReRAM (1T1R) arrays fabricated using 65nm CMOS technology. Our results show bipolar 1T1R arrays can correctly encode 4-bit message data to 7 bit encoded data as well as error position detection with overall 3 fold less power consumption than previously reported unipolar ReRAM crossbar array-based computation. Furthermore, we propose and simulate a peripheral circuit to convert the analog column output from a 1T1R array to single-bit binary output using the Cadence Spectre simulator. Our results pave the way for using a memristor-based fast and scalable hardware solution for encoding decoding of error-correcting codes

Error control coding improves reliability and efficiency of wireless communication systems. This research delves into the latest advancements in error control coding schemes for wireless communication systems, with a specific focus on their application within the domain of Low Power Wide Area Networks (LPWANs) such as Narrowband Internet of Things (NB-IoT) systems, LoRa energy-efficient hardware design, random access control systems, and wireless sensor networks. In the context of LPWANs, particularly NB-IoT systems, we investigate the adaptive coding and modulation (ACM) in NB-IoT systems, which adapts coding rates and modulation techniques to changing channel circumstances. Comprehensive analysis of the literature review shows that the proposed approaches are more energy efficient and less error-prone than fixed coding and modulation schemes. Using Cell Design Methodology (CDM), Single Error Correction (SEC) codes are optimized for energy efficiency. Power and energy efficiency have improved in standard CMOS and CDM logic systems. This impacts IoT devices, memory storage, and security systems. Next, Forward Error Correction (FEC) is examined for ALOHA-based random-access control systems wherein packet loss rate and spectral efficiency metrics are mathematically calculated. FEC is beneficial, especially when time and frequency synchronization diverge. Monte Carlo simulations studied in the literature shows that FEC improves satellite communication systems. This review establishes benefits of FEC, notably in satellite communications systems. In addition, Wireless Sensor Networks (WSNs) error control techniques and network reliability and performance are examined along with Convolutional, Turbo, Low density parity check codes(LDPC), and Polar error correction coding (ECC) methods. We learn about their benefits, drawbacks, and implementation challenges by assessing their efficacy, efficiency, and applicability in wireless sensor networks (WSN) applications. This study further highlights advancements of energy-efficient error control coding when, integrated into network designs alongwith the trade-offs between efficacy and intricacy to help improve wireless communication networks. Finally, this study summarizes current error control coding approaches for wireless communication systems. We provide insights into improving reliability, energy conservation, and efficacy by examining ACM, CDM, FEC, and error correction coding (ECC) across varied domains including LPWAN and IoT technologies with earnest hope to facilitate researchers, engineers, and professionals working in the field of error control coding in wireless communication.

Error correction codes (ECCs) are commonly used in computer systems to protect information from errors. For example, single error correction (SEC) codes are frequently used for memory protection. Due to continuous technology scaling, soft errors on registers have become a major concern, and ECCs are required to protect them. Nevertheless, using an ECC increases delay, area and power consumption. In this way, ECCs are traditionally designed focusing on minimizing the number of redundant bits added. This is important in memories, as these bits are added to each word in the whole memory. However, this fact is less important in registers, where minimizing the encoding and decoding delay can be more interesting. This paper proposes a method to develop codes with 1-gate delay encoders and 4-gate delay decoders, independently of the word length. These codes have been designed to correct single errors only in data bits to reduce the overhead.

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit precomputation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weightcolumn code during the write operation and is designed by replacing 0’s with 1’s at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the oddweight-column code, the implementation based on the proposed SEC-DED code with check bit precomputation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

DRAMs are used as the main memory in most computing systems today. Studies show that DRAMs contribute to a significant part of overall system power consumption. One of the main challenges in low-power DRAM design is the inevitable refresh process. Due to process variation, memory cells exhibit retention time variations. Current DRAMs use a single refresh period determined by the cell with the largest leakage. Since prolonging refresh intervals introduces retention errors, a set of previous works adopt conventional error-correcting code (ECC) to correct retention errors. However, these approaches introduce significant area and energy overheads. In this article, we propose a novel error correction framework for retention errors in DRAMs, called SECRET (selective error correction for refresh energy reduction). The key observations we make are that retention errors are hard errors rather than soft errors, and only few DRAM cells have large leakage. Therefore, instead of equipping error correction capability for all memory cells as existing ECC schemes, we only allocate error correction information to leaky cells under a refresh interval. Our SECRET framework contains two parts: an offline phase to identify memory cells with retention errors given a target error rate and a low-overhead error correction mechanism. The experimental results show that among all test cases performed, the proposed SECRET framework can reduce refresh power by 87.2% and overall DRAM power up to 18.57% with negligible area and performance overheads.

Inspired by the way human brain works, the emerging hyperdimensional computing (HDC) is getting more and more attention. HDC is an emerging computing scheme based on the working mechanism of brain that computes with deep and abstract patterns of neural activity instead of actual numbers. Compared with traditional ML algorithms such as DNN, HDC is more memory-centric, granting it advantages such as relatively smaller model size, less computation cost, and one-shot learning, making it a promising candidate in low-cost computing platforms. However, the robustness of HDC models have not been systematically studied. In this paper, we systematically expose the unexpected or incorrect behaviors of HDC models by developing HDXplore, a blackbox differential testing-based framework. We leverage multiple HDC models with similar functionality as cross-referencing oracles to avoid manual checking or labeling the original input. We also propose different perturbation mechanisms in HDXplore. HDXplore automatically finds thousands of incorrect corner case behaviors of the HDC model. We propose two retraining mechanisms and using the corner cases generated by HDXplore to retrain the HDC model, we can improve the model accuracy by up to 9%.

To improve the reliability of static random access memory (SRAM), error-correcting codes (ECC) are typically used to protect SRAM in the cache. While improving the reliability, we also need additional circuits to support ECC, including encoding and decoding logic. In a high-speed circuit such as a CPU, the L1 cache maintains the same frequency as the CPU, and the decoding of the ECC codes in the cache consumes considerable combinational logic, resulting in limited frequency and performance. This study proposes a high-performance and flexible design scheme with ECC protection in the cache, in which the cache has two working modes: a high-performance mode and a high-reliability mode. The high-performance mode uses simple ECC codes, which can maintain high frequency with low access latency. The high-reliability mode uses more complex ECC codes, which improves the error correction capability and enhances the reliability of the SRAM. To meet the application requirements of different scenarios, the proposed scheme supports the software in switching between the above two modes by configuring the register, which improves the flexibility of the system. The results of synthesis show that the theoretical maximum frequency of proposed ECC design scheme increased from approximately 1.4 GHz in the conventional ECC design scheme to approximately 2.2 GHz. Some of the error correction capability of the high-performance mode is traded off against a 57% increase in frequency. In the high-reliability mode, the error correction capability of the SRAM is enhanced; however, the latency of accessing the cache increases by one cycle.

Efficient error detection in Double Error Correction BCH codes for memory applications

Soft errors caused by radiation particles are becoming an increasingly important issue for memory reliability. Traditionally, Single Error Correction (SEC) codes have been used to correct soft errors. Such codes can correct one error per memory word, but as errors become more frequent they may be insufficient. More complex error correction codes (ECCs) could be used, but they typically require complex decoders which impact memory area and speed. In this paper, the use of Euclidean geometry (EG) Codes for memory applications is studied. The results show that these codes, which provide powerful error correction capabilities, can be implemented efficiently in terms of area and latency.

The conventional error correcting code (ECC) schemes for caches are based on a fixed mapping between cache data words and ECC check bits, and fixed ECC word granularity. This leads to inefficient usage of the ECC check bits. We propose to manage the check bits flexibly for low-cost error protection of last-level caches. The proposed ECC schemes work at the word level, whereas the conventional ECC schemes work at the cache line or set level. The proposed schemes protect only dirty words with ECC check bits using a flexible mapping. Moreover, the proposed schemes utilize variable ECC word granularities. Dirty (modified) words that are unlikely to be modified further before being evicted are collectively protected with a larger ECC word granularity. The proposed schemes reduce DRAM and data bus energy overheads by 28% and 45%, respectively, with the same area overhead as previously proposed competitive schemes. Our schemes show more energy reduction results for multicore systems without noticeable performance degradation.

The transmission of communication signals must not only ensure the speed of transmission, but also ensure the accuracy of transmission. The current research has been able to draw the advantages and disadvantages of the application of different error-correcting codes. However, it is not enough to simply compare transmission performance between different error correction code applications. Therefore, this paper uses MATLAB to simulate the transmission environment of the real channel, analyzes the reception error of short-length data through QPSK coding and IQ modulation, and analyzes the signal transmission using error correction code (Hamming code) and error detection code (even check code). The transmission performances were explored and compared, and their anti-noise interference performance was analyzed. Studies have shown that for short-length data, the error correction method using Hamming code can resist limited noise interference, but it can save bandwidth and increase the proportion of effective signal bits. In the low signal-to-noise ratio case, the method of using even-check code to detect errors has problems. Errors may be generated, and the proportion of effective signal bits is low, but the adaptability to noise is stronger than the previous method. Therefore, it is recommended to select different transmission methods for transmission environments with different signal-to-noise ratio ranges, and the combination of the two may further improve the anti-noise interference capability of signal transmission.

This paper proposes a unified off-chip memory integrity protection scheme, named IVEC. Today, a system needs two independent mechanisms in order to protect the memory integrity from both physical attacks and random errors. Integrity verification schemes detect malicious tampering of memory while error correcting codes (ECC) detect and correct random errors. IVEC enables both detection of malicious attacks for security and correction of random errors for reliability at the same time by extending the integrity verification techniques. Analytical and experimental studies show that IVEC can correct single-bit errors and even multi-bit errors from one DRAM chip within a cache block read without any additional ECC bits, when the integrity verification is also required for security, effectively removing the memory and bandwidth overheads (12.5%) of typical ECC schemes. Alternatively, with parity bits, IVEC can provide even stronger error correction capabilities comparable to the traditional chip-kill correct, still with less overheads. For both cases, IVEC can use standard non-ECC DIMMs.