Microwave connector characterization

Electro-deformation spectroscopy: A unified method for simultaneous electrical and mechanical characterization of single cells

Flexible electronics is a promising technology for wearable applications. The flexible printed thin-film transistor (TFT) circuits, however, often suffer from large process variations and inferior long-term reliability. This paper describes recent progress on robust printed circuits, including a novel design style known as Pseudo-CMOS, which was invented [1] to tackle design challenges for flexible TFT circuits. With post-fabrication tuning capability, Pseudo-CMOS can survive large process variations which are inevitable for the low-cost printing process. Furthermore, degradation of circuit performance, either due to variations or aging, can be recovered by means of an external tuning circuit. The paper also illustrates some design examples of Pseudo-CMOS circuits for applications to energy [2], healthcare [3], biomedical [4], and near-field communication (NFC) tags [5], [6].

Gain an intuitive understanding of jitter and phase noise with this authoritative guide. Leading researchers provide expert insights on a wide range of topics, from general theory and the effects of jitter on circuits and systems, to key statistical properties and numerical techniques. Using the tools provided in this book, you will learn how and when jitter and phase noise occur, their relationship with one another, how they can degrade circuit performance, and how to mitigate their effects - all in the context of the most recent research in the field. Examine the impact of jitter in key application areas, including digital circuits and systems, data converters, wirelines, and wireless systems, and learn how to simulate it using the accompanying Matlab code. Supported by additional examples and exercises online, this is a one-stop guide for graduate students and practicing engineers interested in improving the performance of modern electronic circuits and systems.

Practical Synthesis of High-Performance Analog Circuits presents a technique for automating the design of analog circuits. Market competition and the astounding pace of technological innovation exert tremendous pressure on circuit design engineers to turn ideas into products quickly and get them to market. In digital Application Specific Integrated Circuit (ASIC) design, computer aided design (CAD) tools have substantially eased this pressure by automating many of the laborious steps in the design process, thereby allowing the designer to maximise his design expertise. But the world is not solely digital. Cellular telephones, magnetic disk drives, neural networks and speech recognition systems are a few of the recent technological innovations that rely on a core of analog circuitry and exploit the density and performance of mixed analog/digital ASICs. To maximize profit, these mixed-signal ASICs must also make it to market as quickly as possible. However, although the engineer working on the digital portion of the ASIC can rely on sophisticated CAD tools to automate much of the design process, there is little help for the engineer working on the analog portion of the chip. With the exception of simulators to verify the circuit design when it is complete, there are almost no general purpose CAD tools that an analog design engineer can take advantage of to automate the analog design flow and reduce his time to market. Practical Synthesis of High-Performance Analog Circuits presents a new variation-tolerant analog synthesis strategy that is a significant step towards ending the wait for a practical analog synthesis tool. A new synthesis strategy is presented that can fully automate the path from a circuit topology and performance specifications to a sized variation-tolerant circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel non-linear infinite programming optimization formulation of the circuit synthesis problem via a sequence of smaller optimization problems. Practical Synthesis of High-Performance Analog Circuits will be of interest to analog circuit designers, CADsEDA industry professionals, academics and students.

Solder joint shape optimization and thermal-mechanical reliability improvement for microwave RF coaxial connectors

Due to the rapid growth in the size of designs and Field Programmable Gate Arrays (FPGAs), CAD run-time has increased dramatically. Reducing FPGA design compilation times without degrading circuit performance is crucial. In this work, we describe a novel approach for incremental design flows that both identifies tightly grouped FPGA logic blocks and then uses this information during circuit placement. Our approach reduces placement run-time on average by more than 17% while typically maintaining the design's critical path delay and marginally increasing its minimum channel width and wire length on average. Instead of following the traditional approach of evaluating a circuit's pre-placement netlist, this new algorithm analyzes designs post-placement to detect proximity data. It uses this information to non-aggressively extract heterogeneous cluster groupings from the design, which we call gems, that consist of two to seventeen clusters. We modified VPR's simulated annealing placement algorithm to use our Singularity Placer, which first crushes each cluster grouping into a singularity, to be treated as a single cluster. We then run the annealer over this condensed circuit, followed by an expansion of the singularities, and a second annealing phase for the entire expanded circuit.

This paper presents an approach for analysis of crosstalk effects due to current pulses drawn from voltage supplies in mixed analog-digital CMOS integrated circuits. A test chip has been integrated and mounted in different ways, in order to compare measurements on chips mounted in package and mounted on board. The chip has been extensively simulated, using a realistic model of on-chip and off-chip parasitics, to study what happens on the analog section when digital switching noise is injected. Simulations results indicate that disturbances due to switching currents in digital blocks propagate through interconnection parasitics, and affect analog voltages, degrading circuit performance. Therefore, reduction of interconnection parasitics is essential in mixed-signal high-frequency circuits, such as radio-frequency front-ends. Measurements confirm simulation results

This paper revisits and extends a general linear programming (LP) formulation to exploit multiple knobs such as multi-L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gate</sub> footprint-compatible libraries and post-layout L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gate</sub> -biasing to minimize total leakage power under timing constraints. We minimize positive timing slack for each cell according to its leakage vs. delay sensitivity, so that unnecessary leakage power consumption is saved without degrading circuit performance. A key difference between our work and previous works is that we pre-process timing libraries to estimate the linear relation - in every slew-load condition - between the gate delay and gate length by linear fitting; we then optimize total leakage power by estimating the optimal gate length for each gate using fast linear programming. With a 65GP industry testbed, and directly comparing with commercial tools, we show the QOR and runtime advantages of our method for the multi-L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gate</sub> and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gate</sub> -biasing knobs. We also show a promising application to circuit timing legalization, a problem which frequently arises when implementation and sign off timers differ. Overall, our results show strong viability of LP based estimation and optimization: compared with the commercial tools, we: (1) shift the achievable delay-leakage tradeoff curve in a positive way, and (2) more accurately maintain prescribed timing constraints.

This paper describes the application of a low-voltage scanning electron microscope (SEM) with nanometer-level accuracy for measurement in ultra-large-scale integration (ULSI). Minimum feature sizes of integrated circuits are expected to reach the 100-nm level and below (the nanometer region) in the near future. For the lithography process under that regime, precise critical dimension (CD) control and high resolution of resist patterns will be quite important for device fabrication, because variations in pattern sizes will degrade circuit performance. Therefore, metrology with nanometer-level accuracy is required for device fabrication under the regime. Here, we report on a CD-SEM that operates at 500 V to measure patterns at the 1 Gbit level. We used the S-8840 (Hitachi) to measure holes, lines/spaces, and the calibration standard (Micro-Scale). Several voltages from 500 V to 1000 V were used for the measurements. Static variation of less than 3 nm (3(sigma) ) was obtained in the pitch measurement of the Micro- Scale regardless of the acceleration voltages. For the holes, a lower voltage provided higher accuracy in static measurements. In the nanometer region, resist-pattern sizes microscopically fluctuate to the level of 10 nm due to the polymer characteristics of the resists (nano edge roughness). We could also characterize resist-pattern fluctuations with high accuracy. We compared our measurements with those from an atomic force microscope (AFM) for nanometer-level metrology, and conclude that at present CD-SEMs are more advantageous because of their higher accuracy and throughput.

We report the impact of submicron fully depleted (FD) SOI MOSFET technology on device AC characteristics and the resultant effects on analog circuit issues. The weak DC kink and high frequency AC kink dispersion in FD SOI still degrade circuit performance in terms of distortion and low-frequency noise requirements. These issues raise concerns about FD devices for mixed-mode applications. Therefore, further device optimization such as source/drain engineering is still necessary to solve the aforementioned issues for FD SOI. On the other hand, partially depleted SOI MOSFET with body contact structures provide an alternative technology for RF/baseband analog applications.

A typical field programmable analog array consists of configurable analog arrays (CABs), I/O blocks, an interconnection network and memory registers for device programming. For testing purposes, this FPAA partitioning also applies. Taking advantage of the inherent programmability of the FPAAs, BIST (built-in-self-testing) based scheme is used to obtain an error signal representing the difference between fault free and faulty circuits. A comparison between the various testing methodologies is done in terms of area overhead, circuit performance degradation, fault coverage etc.

As technology scales, Negative Bias Temperature Instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, we first investigate the impact of NBTI on PMOS devices and propose a temporal performance degradation model that considers the temperature variation between active and standby mode. We then discuss the resemblance between NBTI and leakage mechanisms, and find out that the impact of input vector and internal node on leakage and NBTI is different; hence, leakage and NBTI should be optimized simultaneously. Based on this, we study the impact of standby leakage reduction techniques (including input vector control and sleep transistor insertion) on circuit performance degradation considering active and standby temperature differences. We demonstrate the potential mitigation of the circuit performance degradation by these techniques.

Microelectronic realization and circuit properties of a circulator

Technical analysis of intellectual property (IP) is conducted for the purpose of legal protection and product development. A brief review of the process of IP analysis and associated terminology is...

In the design of sequential relay circuits one often has to consider the circuit as a part of a larger system, and one must take into account the nature of the inputs to the circuit. Frequently, the inputs are two-terminal contact networks with one terminal grounded; such inputs will be called simple. This paper examines the formal design techniques as applied to circuits with simple inputs. It is shown that all relays should be considered as secondary, from the point of view of both races and minimization. Several other shortcomings of the present theory are pointed out. Properties of circuits with simple inputs are examined. It is shown that there are flow tables not realizable without races with simple inputs, and that the presently known secondary assignment methods are not applicable to circuits with simple inputs.