Modular Hardware Design with Timeline Types

A representation for specifying the timing constraints of real‐time systems is presented. Four parts of descriptions in a timing constraint: the path of events, timer, types of constraints and quantities of time, are explained. Under the relations among the paths, the hierarchical and network structures can be conducted. The former can be associated with the structure resulting from applying top‐down decomposition in software development. The latter represents the execution dependence of the paths. Based upon these clear and manageable structures, the completeness and consistency of timing constraints specification can be rigorously analysed. Thus, the quality of the specification of timing constraints can be improved during software development. A frame‐like software requirements specification language (FSRSL) is extended to specify timing constraints and the related descriptions in the paper.

This paper describes two methods to specify timing constraints in behavioral VHDL for high-level synthesis purposes. The first method specifies timing constraints on sequences of statements by using predefined procedures. The second method provides support for specification of timing constraints across process borders based on concurrent assert statements on signal events. The paper discusses also an approach to synthesize hardware with timing constraints and concentrates in particular on how to ensure consistency between the behavior of the simulation model and that of the synthesized hardware.

Chapter 14 - Modular and Incremental Design

One of the major challenges in commercializable micro-nano systems development is the high cost and turnaround that are incurred through multiple product-optimization iterations and expensive fabrication processes for specific systems. Development of complex and heterogeneous micro-nano systems, that are only possible through assembly and not by conventional surface machining approaches, are further impeded by lack of standard design rules and off-the-shelf robotic manipulation systems. Dedicated hardware and system specific component designs, although possible, are not commercially viable for addressing the wide range of opportunities that exists in the prevailing micro-nano domain. In this paper, we present an alternative and holistic top-down approach for micro-nano manufacturing using modular part designs and flexible assembly systems. We incorporate, seamlessly, multiple novel algorithms related to microrobotics and scaling of physics, obtained both analytically as well as experimentally; in order to predict, track and control the uncertainty propagation in a typical manufacturing process, in micro-nano scale, throughout production steps including design, machining, setup, assembly, testing etc. We demonstrate, through multiple examples, the implementation of the proposed framework in micro-nano scale manufacturing.

Deceptive path planning (DPP) aims to find a path that minimizes the probability of the observer identifying the real goal of the observed before it reaches. It is important for addressing issues such as public safety, strategic path planning, and logistics route privacy protection. Existing traditional methods often rely on “dissimulation”—hiding the truth—to obscure paths while ignoring the time constraints. Building upon the theory of probabilistic goal recognition based on cost difference, we proposed a DPP method, DPP_Q, based on count-based Q-learning for solving the DPP problems in discrete path-planning domains under specific time constraints. Furthermore, to extend this method to continuous domains, we proposed a new model of probabilistic goal recognition called the Approximate Goal Recognition Model (AGRM) and verified its feasibility in discrete path-planning domains. Finally, we also proposed a DPP method based on proximal policy optimization for continuous path-planning domains under specific time constraints called DPP_PPO. DPP methods like DPP_Q and DPP_PPO are types of research that have not yet been explored in the field of path planning. Experimental results show that, in discrete domains, compared to traditional methods, DPP_Q exhibits better effectiveness in enhancing the average deceptiveness of paths. (Improved on average by 12.53% compared to traditional methods). In continuous domains, DPP_PPO shows significant advantages over random walk methods. Both DPP_Q and DPP_PPO demonstrate good applicability in path-planning domains with uncomplicated obstacles.

We study the problem of providing real-time service to hard and soft real-time messages in wavelength division multiplexing (WDM) optical networks. We propose and evaluate a set of scheduling algorithms which schedule message transmissions in single-hop WDM passive star networks based on specific time constraints. We compare the performances of our algorithms with that of the typical WDM scheduling algorithm which does not consider the time constraint of the transmitted messages by discrete-event simulations and an analytical model. We find that the improvement on real-time performance can be attributed to our scheduling algorithms where the time constraint of messages has been taken into consideration. This study suggests that when scheduling real-time messages in WDM networks, one has to consider not only the problem of resources allocation in the network but also the problem of sequencing messages based on their time constraints.

Password authentication has always been a natural choice for remote access in network applications. Although there have been many protocols of this kind exists today, few have seriously taken into account and exploited the duplex nature of modern communication networks. Given the capability to send and receive messages at the same time, it would be inefficient in terms of communication and computation resources for participants to wait for responses while doing nothing. There have also been a number of researches focus on parallelization of computations in step-oriented protocols. However, these protocols are often highly integrated and no modification is considered secure without rigorously analyzing them again. Thus, system designers who have restrictions and policies set for by their institutions may find that incorporating these protocols a dreadful task. In this paper, we seek to identify the functional modules in password authentication schemes and give a general procedure for generating protocols with these modules. We also give a proof of security for the generalized protocol produced from the procedure. With modular and round-oriented design, we show that flexible infrastructure can be built to provide sound solutions to password authentication in a wide range of hardware/software implementations and computing capabilities.

Modeling embedded real time systems consisting of different components with UML-RT leads to a design model using various diagrams. Sequence diagrams describe possible interactions between system components and may be annotated with specific real time constraints. Statechart diagrams are used for describing each component's behavior. In order to be able to get a consistent model, a consistency concept for different diagram types is needed that takes into account real time constraints. A consistency concept for sequence diagrams and statechart diagrams is presented which focuses on the establishment of timing constraints. Our consistency concept distinguishes between syntactical, semantic and real time consistency and takes into account the influence of processor allocation and scheduling. Using the consistency concept, we describe a method for ensuring the consistency based on worst case execution time analysis of statecharts and schedulability analysis of tasks, thereby enabling a precise answer to the question of consistency.

Specification and verification of timing properties is a critical but error-prone issue in the development of real-time systems. Event-B is a formalism with the aim of modeling and analyzing systems. But it does not directly support the modeling of timing properties. Several studies have extended Event-B to formalize timing properties. These works are mainly concerned with timing constraints between events without the consideration of task-level timing constraints. In this paper, we propose patterns for task-level timing constraints precedence and coincidence. Firstly, we introduce the pattern for task deadline that states timing properties within a task. Then patterns for precedence and coincidence are built on top of this one. Furthermore, we illustrate the application of proposed patterns through the formal development of an example. It shows that the patterns can be integrated with Event-B models smoothly by the refinement. Our patterns can be potentially applicable to a wide range of modeling safety critical real-time systems. Additionally, our work provides a reference for the specification of other task-level timing constraints, e.g., exclusion and sub-occurrence.

With the development of industrialization, application of pipe is becoming more and more. The traditional pipe cutting method cannot meet the market demand. CNC cutting can make up for the deficiency of traditional manual cutting, a kind of cutting robot control system based on Trio motion controller is designed in this paper, the design of hardware and software is done. The system uses modular design, greatly improving the efficiency of software development, so that the system has good openness and portability. The use of double CPU mode can ensure the reliability and processing speed. This system can be used in cutting robot.

Hardware design languages (HDLs) allow computer hardware to be described in sufficient detail to be simulated and built, such a description being at a sufficiently high level of abstraction to make the complete design readily intelligible to anyone skilled in that language. A number of HDLs have been developed and are in use in IBM. To date, no overwhelming case can be made for choosing any one HDL over the others. The major trends in HDL are discussed. Several examples of HDLs are presented in some detail. VHDL, the yet-to-be released HDL which is to serve as a front end to the U.S. Government's Very High Speed Integrated Circuits program, is among these.

We show that the action systems framework combined with the refinement calculus is a powerful method for handling a central problem in hardware design, the design of pipelines. We present a methodology for developing asynchronous pipelined microprocessors relying on this framework. Each functional unit of the processor is stepwise brought about which leads to a structured and modular design. The handling of different hazard situations is realized when verifying refinement steps. Our design is carried out with circuit implementation using speed-independent techniques in mind.

This study investigates the use of science-based experimental methods to enhance creativity in early childhood at RA Roihanul Jannah. The research involved 31 students actively engaging in science learning through experiments. A qualitative approach was adopted, focusing on Group B teachers and the principal as informants. Data were collected through observation, interviews, and documentation from July to August 2024. The findings indicate that the experimental method effectively promotes scientific understanding, curiosity, and problem-solving skills among children. It also enhances fine and gross motor skills through hands-on activities. However, challenges include the need for specific materials and time constraints. The study concludes that incorporating experimental methods in early childhood education significantly fosters creativity and engagement in science.

In this paper, we focus on tasks offloading over two tiered mobile cloud computing environment. We consider several users with energy constrained tasks that can be offloaded over cloudlets or on a remote cloud with differentiated system and network resources capacities. We investigate offloading policy that decides which tasks should be offloaded and determine the offloading location on the cloudlets or on the cloud. The objective is to minimize the total energy consumed by the users. We formulate this problem as a Non-Linear Binary Integer Programming. Since the centralized optimal solution is NP-hard, we propose a distributed linear relaxation heuristic based on Lagrangian decomposition approach. To solve the subproblems, we also propose a greedy heuristic that computes the best cloudlet selection and bandwidth allocation following tasks' energy consumption. We compared our proposal against existing approaches under different system parameters (e.g. CPU resources), variable number of users and for six applications, each having specific traffic pattern, resource demands and time constraints. Numerical results show that our proposal outperforms existing approaches. We also analyze the performance of our proposal for each application.

Designing efficient, application-specialized hardware accelerators requires assessing trade-offs between a hardware module’s performance and resource requirements. To facilitate hardware design space exploration, we describe Aetherling, a system for automatically compiling data-parallel programs into statically scheduled, streaming hardware circuits. Aetherling contributes a space- and time-aware intermediate language featuring data-parallel operators that represent parallel or sequential hardware modules, and sequence data types that encode a module’s throughput by specifying when sequence elements are produced or consumed. As a result, well-typed operator composition in the space-time language corresponds to connecting hardware modules via statically scheduled, streaming interfaces. We provide rules for transforming programs written in a standard data-parallel language (that carries no information about hardware implementation) into equivalent space-time language programs. We then provide a scheduling algorithm that searches over the space of transformations to quickly generate area-efficient hardware designs that achieve a programmer-specified throughput. Using benchmarks from the image processing domain, we demonstrate that Aetherling enables rapid exploration of hardware designs with different throughput and area characteristics, and yields results that require 1.8-7.9× fewer FPGA slices than those of prior hardware generation systems.