New concepts of worst-case delay evaluation in asynchronous VLSI SoC

Power density and energy dissipation of digital IC's has become one of the main concerns during the recent years. With the increased usage of battery powered devices, ubiquitous computing, and increase in implantable biomedical applications, enhancing energy efficiency of digital systems is one of the key research areas in digital IC design. For applications with a low demand on throughput, sub-threshold digital operation is one of the promising techniques for ultra-low energy operation. Moreover, global energy minimum operating point of a digital static CMOS circuit, if exists, is in the sub-threshold regime; thus, realizing global minimum energy operation. This doctoral dissertation presents different energy efficiency enhancement methods for sub-threshold digital CMOS circuits. First, a high level sub-threshold energy model is developed for rapid characterization of digital circuits. Model accuracy is validated with measurements of a circuit that was fabricated in 0.18 µm process, and with simulations for smaller feature sized technologies. Second, this model is applied to compare the energy efficiency of synchronous and asynchronous circuits. It is shown that with a suitable external completion detection mechanism, energy efficiency of asynchronous circuits in the sub-threshold regime is better than the synchronous counterparts. Process selection to minimize energy dissipation is investigated. Moreover, it is shown that with the correct choice of process options, migrating to a smaller feature sized technology increases the energy efficiency of a circuit. Architectural modifications such as parallelism, pipelining, and folding are also explored and applied to reduce energy dissipation. Finally, a current sensing completion detection system is proposed and implemented for sub-threshold asynchronous circuits. Design flows for de-synchronization of synchronous circuits are presented for various cases with detailed explanations of sub-blocks of the completion detection system. As a proof of concept example, a self-timed cardiac event detector is implemented in a 65 nm CMOS process.

We present various 4-bit /spl times/ 4-bit unsigned multipliers designed using the delay-insensitive null convention logic (NCL) paradigm. They represent bit-serial, iterative, and fully parallel multiplication architectures. NCL is a self-timed logic paradigm in which control is inherent in each datum. NCL follows the so-called weak conditions of Seitz's delay-insensitive signaling scheme. Like other delay-insensitive logic methods, the NCL paradigm assumes that forks in wires are isochronic. NCL uses symbolic completeness of expression to achieve delay-insensitive behavior. Simulation results show a large variance in circuit performance in terms of power, area, and speed. This study serve as a good reference for designers who wish to accomplish high-performance, low-power implementations of clockless digital VLSI circuits.

Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL convention logic (NCL) and traditional clocked Boolean logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 μm process shows that a pseudo-random number generator implemented with NCL generates 23 dB less substrate noise compared to the equivalent synchronous design. In a larger scale digital circuit, the substrate noise improvement offered by an asynchronous 8051 processor over its synchronous counterpart was nearly 10 dB. The effect of this substrate noise on an analog circuit was explored with a delta-sigma modulator (DSM) example. The signal-to-noise ratio performance of a second order DSM was not affected by the substrate noise from the NCL 8051 processor while it experiences up to 15 dB degradation when the CBL 8051 processor is clocked near integer multiples of the DSM sampling frequency.

With Cyber warfare, detection of hardware Trojans, malicious digital circuit components that can leak data and degrade performance, is an urgent issue. Quasi‐Delay Insensitive asynchronous digital circuits, such as NULL Convention Logic (NCL) and Sleep Convention Logic, also known as Multi‐Threshold NULL Convention Logic (MTNCL), have inherent security properties and resilience to large fluctuations in temperatures, which make them very alluring to extreme environment applications, such as space exploration, automotive, power industry etc. This paper shows how dual‐rail encoding used in NCL and MTNCL can be exploited to design Trojans, which would not be detected using existing methods. Generic threat models for Trojans are given. Formal verification methods that are capable of accurate detection of Trojans at the Register‐Transfer‐Level are also provided. The detection methods were tested by embedding Trojans in NCL and MTNCL Rivest‐Shamir‐Adleman (RSA) decryption circuits. The methods were applied to 25 NCL and 25 MTNCL RSA benchmarks of various data path width and provided 100% rate of detection.

Predictive performance models are used increasingly throughout the phases of the software engineering lifecycle of distributed systems. However, as systems grow in size and complexity, building models that accurately capture the different aspects of their behavior becomes a more and more challenging task. The challenge stems from the limited model expressiveness on the one hand and the limited scalability of model analysis techniques on the other. This chapter presents a novel methodology for modeling and performance analysis of distributed systems [Kounev, 2006]. The methodology is based on queueing Petri nets (QPNs) which provide greater modeling power and expressiveness than conventional modeling paradigms such as queueing networks and generalized stochastic Petri nets. Using QPNs, one can integrate both hardware and software aspects of system behavior into the same model. In addition to hardware contention and scheduling strategies, QPNs make it easy to model software contention, simultaneous resource possession, synchronization, blocking and asynchronous processing. These aspects have significant impact on the performance of modern distributed systems. To avoid the problem of state space explosion, our methodology uses discrete event simulation for model analysis. We propose an efficient and reliable method for simulation of QPNs [Kounev & Buchmann, 2006]. As a validation of our approach, we present a case study of a real-world distributed system, showing how our methodology is applied in a step-by-step fashion to evaluate the system performance and scalability. The system studied is a deployment of the industry-standard SPECjAppServer2004 benchmark. A detailed model of the system and its workload is built and used to predict the system performance for several deployment configurations and workload scenarios of interest. Taking advantage of the expressive power of QPNs, our approach makes it possible to model systems at a higher degree of accuracy providing a number of important benefits. The rest of this chapter is organized as follows. In Section 2, we give a brief introduction to QPNs. Following this, in Section 3, we present a method for quantitative analysis of QPNs based on discrete event simulation. The latter enables us to analyze QPN models of realistic size and complexity. In Section 4, we present our performance modeling methodology for distributed systems. The methodology is introduced in a step-by-step

The design of asynchronous sequential circuits is commonly related to the problem of observing some specific timing constraints to avoid unreliable behaviour. State assignment and hazard-free construction of the combinational circuits for the state transition equations are the most essential topics to investigate. They contribute significantly to the design, particularly in comparison with that of synchronously operated systems. On the other hand, the application of digital circuitry for solving control tasks implies more and more asynchronous interaction between the controller and the controlled unit, and also the use of modern, highly-integrated modules. This paper investigates the possibility of applying arbitrarily chosen, but unique, codes for state assignments, using l.s.i. memories and programmable logic arrays for implementing more complex asynchronous sequential circuits than is possible with discrete or s.s.i/m.s.i. components. A basic model is derived to describe the time properties of such matrix arrays, and design rules are established to decide easily by some simple measurements, if a given module may be used in that application. The results of a broad investigation into available memories and field-programmable logic arrays show that reliable asynchronous sequential circuits may be implemented without having hazard problems and the need for special state-assignment procedures.

Asynchronous circuits have potential advantages of higher speed and lower power consumption compared to their synchronous counterparts, but their poor CAD support is a major issue limiting adoption. In this paper, we present an integrated timing and power analysis engine capable of handling large asynchronous circuits. For timing, we introduce the notion of performance and correctness slack for asynchronous circuits; for power, we compute both the static and dynamic components. We provide a hierarchical approach to constructing the event-dependency graph, and use the Galois framework for parallelization to achieve fast runtime. The net result is Cyclone, a fast and accurate engine for both static timing and power analysis of asynchronous circuits.

The asynchronous circuits from digital electronics are modeled by Boolean asynchronous dynamical systems, consisting in functions Φ : {0, 1}n → {0, 1}n that iterate their coordinates Φ1, ..., Φn independently on each other. The purpose of this work is to give a Lyapunov-Lagrange type theorem that characterizes the invariance of the sets A ⊂ {0, 1}n in the case of these systems.

Automated synchronous-to-asynchronous circuit conversion can be considered as one area of clockless design style, which is becoming more and more interesting for synchronous designers with lack of knowledge and experience in the real asynchronous circuit design. Another reason why it is becoming so interesting is that the languages and design styles for specification of asynchronous circuits require a learning curve to understand, become proficient with them, and to use them effectively. Hence, numerous approaches for automated conversion of synchronous circuits into their asynchronous counterparts have been proposed in recent years. The main reason is the exploitation of the often claimed advantages of asynchronous circuits, especially their lower power consumption. This paper surveys some of the available well-known synchronous-to-asynchronous conversion techniques and tries to present both their positive and negative properties.

In this paper a new formal model is presented which allows the uniform representation of the discrete functional and timing behavior of arbitrary MOS transistor circuits. Algorithms are presented to automatically extract the model from transistor netlists and to transform it into VHDL simulation descriptions. The accuracy of the VHDL simulation is sufficient for a detailed functional and timing analysis of digital circuits, although the runtime is considerably reduced. The model is well suited for formal verification approaches since it is based on formalized timed transition systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Industrial Revolution 4.0 relates to many digital devices, machines or applications that&nbsp;integrates&nbsp;with internet and needs to be controlled on one or two of its parameter values regarding the importance of output in order to function correctly. Those parameter&nbsp;values&nbsp;have standard limitation and essential automation procedures should be taken&nbsp;for&nbsp;keeping&nbsp;the good operation of devices, machines or system.&nbsp;Controlling a limit based parameter is difficult if done manually and needs full concentration. Digital monitoring circuit would be very helpful for doing that controlling with the support of digital technology development nowadays. The usage of monitoring circuit currently applied in many fields especially for monitoring the condition of a patient in a hospital bed. Regarding health management and digitalization, digital monitoring circuit becomes very important and needs continued improvement. Based&nbsp;on&nbsp;the&nbsp;problem above, this paper is conducted a research to design a&nbsp;digital&nbsp;monitoring&nbsp;circuit for the purpose of controlling a limit based parameter value for patient medication.&nbsp;The&nbsp;research methodology contains literature study,&nbsp; analysis&nbsp;and&nbsp;logic simulation. The outcome derives a reliable digital logic circuit that could be implemented into&nbsp;a&nbsp;real&nbsp;digital&nbsp;circuit or Integrated Circuit (IC) components to help people controlling the condition of a patient based on limit parameter value and support medical industries to improve their devices, machines or system performance to work more accurately and give out best medical services.

The growing variability and complexity of advanced CMOS technologies makes the physical design of clocked logic in large Systems-on-Chip more and more challenging. Asynchronous logic has been studied for many years and become an attractive solution for a broad range of applications, from massively parallel multi-media systems to systems with ultra-low power & low-noise constraints, like cryptography, energy autonomous systems, and sensor-network nodes. The objective of this embedded tutorial is to give a comprehensive and recent overview of asynchronous logic. The tutorial will cover the basic principles and advantages of asynchronous logic, some insights on new research challenges, and will present the GALS scheme as an intermediate design style with recent results in asynchronous Network-on-Chip for future Many Core architectures. Regarding industrial acceptance, recent asynchronous logic applications within the microelectronics industry will be presented, with a main focus on the commercial CAD tools available today.

NULL Convention Logic (NCL) is a symbolically complete logic which expresses process completely in terms of the logic itself and inherently and conveniently expresses asynchronous digital circuits. The traditional form of Boolean logic is not symbolically complete in the sense that it requires the participation of a fundamentally different form of expression, time in the form of the clock, which has to be very carefully coordinated with the logic part of the expression to completely and effectively express a process. We introduce NULL Convention Logic in relation to Boolean logic as a four value logic, and as a three value logic and finally as two value logic quite different from traditional Boolean logic. We then show how systems can be constructed entirely in terms of NULL Convention Logic.

PurposePower consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits.Design/methodology/approachIn this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment.FindingsExperimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits.Originality/valueThe proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

Among other things, field-programmable gate arrays (FPGAs) available today contain numerous bit-serial transceivers for communication purposes. Unlike analog modulation schemes, such as quadrature amplitude modulation, bit-serial communication is relatively easy to implement in digital hardware, and is thus usually used for inter FPGA communication. In this view, only the data rate and frequency limit the bandwidth of the circuit. In order to overcome the bandwidth limit, this research proposes a pulse-width modulation (PWM) scheme for data transmission. The information is coded by modulating the length of the high and low voltage parts of the pulse. Although this approach is not new, existing PWM modulators have unsatisfactorial data rates due to their synchronous implementation nature. Therefore, this research implements both the modulator and demodulator by using asynchronous logic. The result is a proof-of-concept comprising two Terasic DE2-70 development boards and a 1 m coaxial cable. Both the PWM modulator and demodulator run at 333 MHz, and pulses are transmitted every 3 ns. Each pulse carries 3 to 4 bits of data. The experimental results indicate an achievable data rate of one gigabit per second, which is about 50 % larger than the FPGA's handbook states.