On the fault coverage of high-level test derivation methods for digital circuits

Finite state machines (FSM) are widely used in testing and verification of discrete event and hybrid systems. In order to guarantee fault coverage, various fault models and formal methods are utilized ranging from classical finite state machines (FSM) to logic circuits. The main problem for deriving an FSM-based test suite is the size of an FSM for real digital circuits, and thus, test engineers prefer to randomly derive a prefix of a test sequence and later on extend it with tests for hard detectable faults of a corresponding logic circuit. Usually at the latter step test sequences detecting hard detectable stuck-at faults are considered. In this paper, we are concerned about single functional faults, namely, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{a},\boldsymbol{b}-\mathbf{faults}$</tex> , of a system of Boolean functions of the combinational part of a sequential circuit such as deleting a variable or a cube in a SoP which represents the ON-set or the OFF-set of a corresponding Boolean function and experimentally evaluate fault coverage of a corresponding complete test suite with respect to fault coverage of tests returned by other methods. The experimental results show high fault coverage of test suites complete with respect to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{a},\boldsymbol{b}-\mathbf{faults}$</tex> and thus, it can be recommended to utilize such a test suite instead of a complete FSM-based test suite or to extend randomly generated test sequences for detecting <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{a},\boldsymbol{b}-\mathbf{faults}$</tex> not killed with the prefix.

Current signature analysis of induction motor becomes very much popular for its Condition monitoring purpose. Most of these studies in recent years are focused on hardware. Though, to build an experimental set-up for fault emulating machines is not an easy task. It involves too much cost and risk of damage. Moreover, it is not possible to create different types of faults in the same machine. In this paper an accurate but simple model of 3-phase Induction motor is being proposed which describes the machine at low frequency as well as at high frequency for different types of fault situations. The model, based on DM, CM characteristics of the machine, is well suited for power frequency (50 Hz) and high frequency applications like adjustable speed drives (ASDs). A mechanical model of a three-phase induction machine is incorporated to this electrical model to make a universal model of dynamic squirrel cage induction motor for overall simulation. The proposed model has the feature to incorporate different types of electrical fault like, stator inter-turn fault, phase-to-phase and phase-to ground insulation fault etc. The premature conditions of the above faults can also be emulated.

A combined image processing and Nearest Neighbor Algorithm tool for classification of incipient faults in induction motor drives

A general framework and a method for model based diagnosis are suggested. In the framework, faults and modeling of faults are formally described. Then the method is used to construct a diagnosis system based on a structure of hypothesis tests. Using these principles, it is possible to diagnose a large variety of different types of faults. The framework and the method are applied to the design of a diagnosis system for an automotive engine. This application clearly shows the strength of these principles because several different types of sensor faults and leakage need to be diagnosed. The resulting diagnosis system is demonstrated using experiments on a real automotive engine.

Research demonstrated that faults seeded mutation using operators can be representative of faults in real systems. In this paper, we study the relationship between the different operators used to insert mutants in the fault domain of the system under test and the effectiveness of different state machine test suites at killing those mutants. We are particularly interested in the effectiveness of two interrelated state machine testing strategies at finding different types of faults. Those are the round-trip paths strategy and the transition tree strategy. Using empirical evaluation, we compare the effectiveness of more than two thousand unique test suites at killing mutants seeded using eight different mutation operators. We perform experiments on four experimental objects and provide qualitative analysis of the results. We conclude that neither of the two studied strategies is more effective than the other at killing a certain type of mutants. However, the structure of the finite state machine and the nature of the system under test affect the type of faults detected by the different testing strategies.

Occurrence of unwanted resistance at terminal of IGBTs is a type of Incipient faults which occurs in 3-phase voltage source Inverter. This type of faults does not trigger the protective circuit and in due course of time leads to severe faults. The present work had made an attempt to identify this type of faults related to two IGBTs in the VSI scheme. Rigorous simulation is done with different cases of faults in a PSIM software platform. The current profiles obtained from the simulation are processed by data processing tools to obtain Mean Current vector (MCV). A two phase reference frame shows the distribution of MCV for different types of faults. The distribution is found to follow a particular pattern. This has encouraged the authors to use SVM classifier for analyzing the distributed pattern and classify different types of faults.

The development of differential fault analysis (DFA) techniques and mechanisms to inject faults into cryptographic circuits brings with it the need to use protection mechanisms that guarantee the expected level of security. The AES cipher, as a standard, has been the target of numerous DFA techniques, where its security has been compromised through different formulations and types of fault injections. These attacks have shown vulnerabilities of different AES implementations and building blocks. Consequently, several solutions have been proposed that provide additional protection to cover the identified vulnerabilities. In this paper, an extensive analysis has been carried out covering the existing fault injection techniques, the types of faults, and the requirements needed to apply DFA. Additionally, an analysis of the countermeasures reported in the literature is also presented, considering the protection provided, the type of faults considered, and the coverage against fault attacks. The eight different types of fault that allow us to perform DFAs on the AES cipher have been differentiated, as well as the vulnerabilities of the cipher. On the other hand, two comparisons have been made considering frequency penalty vs. area and fault coverage vs. area and frequency overhead. A metric has been proposed to compare the fault coverage of all the proposed solutions. To conclude, a final analysis is presented discussing the key aspects when choosing a particular solution and the possible development of new countermeasures to provide further protection against DFA.

Extended finite state machines (EFSMs) are widely used when deriving tests for checking the functional requirements for software implementations. However, the fault coverage of EFSMbased tests covering appropriate paths, variables, etc., remains rather obscure. Furthermore, these tests are known be incapable of detecting many functional faults frequently occurring in EFSM-based implementations. In this paper, an approach is proposed for deriving complete tests with the help of a proper Java EFSM implementation. Since the software is based on a template, the faults turn directly into EFSM faults. The method proposed here makes it possible to derive test suites that can detect functional faults. In the first step, the EFSM-based test suite derived by a well-known method is checked for completeness with respect to the faults generated by the μJava tool. Then, each undetected fault is easily mapped into an EFSM mutant. In the next step, some FSM abstraction is used to derive a distinguishing sequence for two finite-state machines (if such a sequence exists), which is added to the current test suite. The test derived in this way is complete with respect to the faults generated by μJava. If the corresponding FSM derived by EFSM modeling is too complex or no such FSM can be derived, the resulting test suite can be incomplete. However, the experiments performed by us clearly show that the original test suite extended by distinguishing sequences can detect many functional faults in software implementations when the given EFSM is used as a specification for the system.

Extended Finite State Machines (EFSMs) are widely used when deriving tests for checking functional requirements for software implementations. However, the fault coverage of tests covering appropriate paths, variables, etc. of the specification EFSM, remains rather obscure and such tests do not detect many functional faults in EFSM implementations. In this paper, an approach is proposed for deriving complete tests with respect to functional faults of a proper Java EFSM implementation. First, an initial test suite derived against the specification EFSM is checked with respect to faults generated by a µJava tool. Since the EFSM software implementation is template based, each undetected fault can be easily mapped into a mutant EFSM of the specification machine. Thus, a distinguishing sequence is derived for two Finite State Machines modeling two EFSMs instead of deriving such a sequence for two programs. If the corresponding FSMs are too complex or cannot be completely derived, a test suite can be incomplete. However, the performed experiments clearly show that a test suite extended by such distinguishing sequences detects much more functional faults in software implementations of a system whose behaviour is described by the given EFSM.

Guest Editorial: Special Section from the 11th International Conference on Quality Software (QSIC 2011)

We propose a new batch bioprocess monitoring approach which combines the Gaussian mixture model (GMM) with the multiway analysis in localized discriminant embedding subspace for detecting and classifying different types of faults. Due to the inherent process multimodality within abnormal points, the capability of traditional multimay locality preserving projection (MLPP) is degraded. For the routine bioprocess operation with abnormal events, GMM is used to partition the training set with various types of faults into different clusters. Three localized distance matrices reflecting the relationships of nearby points are then computed. The extracted leading discriminant embedding directions can not only separate the normal and faulty data by maximizing the distance among nearby data points from different clusters, but also preserve the intrinsic geometrical structure within the multiple faulty clusters by minimizing the small distance and penalizing the large distance among neighboring data from the same cluster. The newly developed multiway localized discriminant embedding (MLDE) approach is applied to two test scenarios in the fed-batch penicillin fermentation process and compared with the conventional MLPP method. The results demonstrate that the MLDE approach is superior to the MFDA method in detecting abnormal events and classifying different types of faults in fed-batch process with higher accuracy and sensitivity.

Mutation analysis is extensively used for the comparison of state-based testing methods that work from a finite state machine (FSM); In this thesis, we report on results from an experiment during which we compared different mutation operators used to generate FSM mutants. We randomly generated multiple synthetic FSMs and selected real-world FSMs; We created all the possible mutants from a complete set of FSM mutation operators; We generated multiple test suites using a pool of test paths; We executed all those test suites on FSM mutants while using different types of oracles, and compared mutation operators using a metric we define. Results help us identify mutation operators that lead to easy-to-reveal faults, possibly too easy to help discriminate between test suite construction techniques, as well as study the impact of various oracle strategies. We have developed a tool infrastructure called μFSM that automates the whole process of this experiment.

Verification and test are critical phases in the development of any hardware or software system. This article focuses on black box testing of the control part of hardware and software systems. Black box testing involves specification, test generation, and fault coverage. Finite state machines (FSMs) are commonly used for specifying controllers. FSMs may have shortcomings in modeling complex systems. With the introduction of X-machines, complex systems can be modeled at higher levels of abstraction. An X-machine can be converted into an FSM while preserving the level of abstraction. The fault coverage of a test sequence for an FSM specification provides a confidence level. We propose a fault coverage metric for an FSM specification based on the transition fault model, and using this metric, we derive the coverage of a test sequence. The article also presents a method which generates short test sequences that meet a specific coverage level and then extends this metric to determine the coverage of a test sequence for an FSM driven by an FSM network. We applied our FSM verification technique to a real-life FSM, namely, the fibre channel arbitrated loop port state machine, used in the field of storage area networks.

Minimizing Characterizing sets

Until now, simulation has been the primary approach for the functional verification of register transfer level (RTL) circuit descriptions written in a hardware description language (HDL). A finite state machine (FSM) coverage test can find all the bugs in a FSM design. However, this is impractical for large designs because of the state explosion problem. In this paper, we modify the higher-level FSM models used in other applications to replace the FSM model in the FSM coverage test. The state transition graphs (STGs) can be significantly reduced in this model, so that the complexity of the test becomes acceptable even for large designs. This model can be easily extracted from the original HDL code automatically, with little computation overhead. Experimental results show that it is indeed a promising functional test for FSMs.