Optical link ASICs for LHC upgrades

Herein, we propose a 25 Gb/s (12.5 Gbaud/s) 4-level pulse amplitude modulation (PAM-4) vertical cavity surface emitting laser (VCSEL) diode driver in TSMC 90 nm CMOS technology. In the VCSEL driver, an equalizer was designed using an edge peak generator to enhance the rising and falling edges of the data signal. The VCSEL driver can combine two 12.5 Gb/s non-return-zero (NRZ) input signals as a 25 Gb/s PAM-4 output current signal to drive a VCSEL diode. For the VCSEL diode driver, the total modulation current is 9.2 mA, the power consumption is 87.47 mW, and the chip size is 0.49 mm×0.49 mm.

The phase 1 upgrade of the ATLAS [1] pixel detector will be done by inserting a fourth pixel layer together with a new beampipe into the recent three layer detector. This new detector, the Insertable B-Layer (IBL) should be integrated into the recent pixel system with as few changes in services as possible, but deliver some advantages over the recent system. One of those advantages will be a new data transmission link from the detector modules to the off-detector electronics, requiring a re-design of the electro-optical converters on the off-detector side. First ideas of how to implement those, together with some ideas to reduce cost by increasing the systems throughput are discussed.

An implementation of a highly efficient spatiotemporal vertical‐cavity surface‐emitting laser (VCSEL) model in the circuit simulation environment of Cadence is presented. The VCSEL model, based on a set of modified rate equations, is written in Verilog‐A. It enables the association of the VCSEL model with transistor‐level models of the driver and detector circuits. Furthermore, the spatiotemporal nature of the model allows the generation of multimode responses and corresponding far‐field intensity profiles, which can be used to investigate fibre coupling and propagation mechanisms. An optimization of the VCSEL drive signal performed using the built‐in optimizer of Cadence is presented. © 2003 Wiley Periodicals, Inc. Microwave Opt Technol Lett 38: 304–308, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.11044

Datacenters demand higher speed vertical cavity surface emitting laser (VCSEL) based optical interconnects at low-power consumption. As a potential technology enabler, this paper presents a wide-bandwidth and energy-efficient multilevel pulse-amplitude-modulation (PAM) VCSEL driver implemented in an InP 0.25 μm double-heterojunction bipolar transistor (DHBT) technology. The operational bandwidth of the driver is verified and error-free electrical data transmission up to 56 Gbps PAM-2 and 100 Gbps PAM-4 is demonstrated at a driver energy consumption less than 2 pJ/bit. The driver is integrated and tested with an in-house fabricated 850 nm VCSEL. Error-free 56 Gbps PAM-4 optical transmission at a transmitter energy consumption of 3.7 pJ/bit is demonstrated without equalization. This is the highest data rate reported for an integrated PAM-4 modulated VCSEL transmitter, while being the most energy efficient above 40 Gbps operation. Moreover, the VCSEL driver offers a pre-emphasis feature at PAM-2 operation for improved link throughput and receiver sensitivity.

The upgrade for ATLAS detector will undergo different phase towards super-LHC. The first upgrade for the Pixel detector will consist of the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (LHC phase-I upgrade). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of 3.3 cm. The IBL will require the development of several new technologies to cope with increase of radiation or pixel occupancy and also to improve the physics performance which will be achieved by reducing the pixel size and of the material budget. Three different promising sensor technologies (planar-Si, 3D-Si and diamond) are currently under investigation for the pixel detector. An overview of the project with particular emphasis on pixel module is presented in this paper.

Silicon Sensor Technologies for the ATLAS IBL Upgrade

The ATLAS collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

A CMOS optical fibre transmitter front-end with an analogue predistortion technique is proposed for reducing laser nonlinearity distortion to achieve broadband linearisation of radio frequency (RF) optical fibre communication systems. The technique uses a nonlinearity having the inverse transfer characteristic of the directly modulated vertical cavity surface emitting laser (VCSEL). The analogue predistortion lineariser comprises a linear and a non-linear transconductance differential amplifier. The combined linear and non-linear transconductance differential amplifiers provide the transfer characteristic to counteract the characteristic of the VCSEL laser diode. The post-layout simulation of the linearity of RF optical fibre systems using the predistortion linearisation technique shows 12dBm improvement. The integrated CMOS optical fibre transmitter circuit with the predistortion lineariser is being implemented using the austriamicrosystems (AMS) 0.35μm CMOS technology.

A Vertical Cavity Surface Emitting Laser (VCSEL) driver in 65nm CMOS selectively-enables parallel low-power CMOS drivers to shape the output current waveforms and compensate VCSEL nonlinearities. The CMOS waveform-shaping drivers are AC-coupled allowing them to operate from a 1V supply to save power, while parallel low-frequency paths provide programmable DC biasing from a 3V supply. The measured VCSEL driver is able to achieve 15Gb/s with up to 5.1dBm OMA at a total power dissipation of 60mW, or 2.1dBm OMA at 28mW corresponding to 1.9pJ/bit. The driver occupies 250×160μm including the on-die AC-coupling.

A 4-channel Vertical Cavity Surface Emitting Laser (VCSEL) driver array is designed in a 0.18μm CMOS technology. Simulated results show that each channel works at 10Gb/s (12.5Gb/s max) under a supply voltage of 1.8 V. Thus, aggregated total capacity of 40 Gb/s can be obtained from 4 channels. The power dissipation of each channel is only 50mW. To decrease the fall time of the output waveform, C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> A (Capacitively Coupled Current Amplifier) technique [1]is exploited. The VCSEL driver can be used in optical inter-connections between high speed chips.

Commissioning of the read-out driver (ROD) card for the ATLAS IBL detector and upgrade studies for the pixel Layers 1 and 2

During the first LHC long shutdown (2013/14) a new innermost pixel layer will be added to the present ATLAS Pixel Detector. The Insertable B-Layer (IBL) is a high-reliability, ultra light and radiation hard Pixel Detector assembled with 3D n-in-p and planar n-in-n pixel sensors. Facing the effects of increased luminosity and radiation damage, IBL is expected to improve the b-tagging efficiency, help with pattern recognition performance and add tracking precision with respect to the current detector. Single and double chip modules are loaded on local mechanical support, in the form of 14 staves arranged in cylindrical barrel around the beam pipe. The production of the modules has already started, aiming for a total production of 24 staves including spares. Systematic Quality Assurance (QA) and Quality Control (QC) plans concerning modules, staves and flex from production to final assembly have been put in place. QA is performed in several collaborating institutes and final validation before installation in the ATLAS experiment will be carried out at CERN. Dedicated set-ups have been constructed in order to perform the full chain of QAlQC tests on the production staves. A CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> cooling system is used to cool the pixel modules down to -35°C and an electronic chain similar to the final one has been developed. Furthermore a linear motion system carrying two 241 Am sources with an activity of 41 MBq each is mounted over the stave in order to perform a final characterization of the sensor's performance. The realization of source scans on the 24 production staves permits to analyze the response of sensors to radiation, to easily identify dead pixels, and to provide data for an eventual re-calibration of the charge calibration. The setup and first results obtained on prototype staves are described in detail.

We describe the implementation of one channel of an optoelectronic orientation enhancement algorithm based on a neurally inspired algorithm. An 8/spl times/8 VCSEL (Vertical Cavity Surface Emitting Laser) array, hybridized to CMOS driver circuits, transmits a contrast-enhanced image that would be computed in the early stages of visual processing. A diffractive optical element (DOE) generates a projective field which reinforces pixels of a preferred orientation. A CMOS receiver integrates correlated pulses to produce high output in frequently activated areas. Data from a one channel system shows orientation enhancement.

This letter presents a feedforward optical power control scheme for automotive 150-Mb/s vertical-cavity surface-emitting laser (VCSEL) transmitters. The bias current exhibits a second-order dependence upon temperature, while the modulation current is provided with a piecewise linear compensation of temperature variations. The resulting VCSEL modulation performance was analyzed in detail and experimentally validated. Over the harsh automotive temperature range from -40°C to 105°C, a high extinction ratio was maintained despite very tight tolerances on pulsewidth distortion (PWD); the variation of the emitted optical power was measured to be less than 1.2 dB, while maintaining an extinction ratio better than 12 dB and a PWD less than ±2%.

An integrated laser diode driver for multi-junction vertical-cavity surface-emitting laser (VCSEL) arrays is presented in this brief. The driver chip, fabricated in 180nm bipolar-CMOS-DMOS (BCD) process, working under 12V supply, can pump more than 8A peak current into a triple-junction VCSEL array, producing up to 20.3W optical pulses. Measured optical pulses have tunable widths from 276ps to 2352ps with 120ps/160ps rise/fall time. When emitting 10MHz-frequency 960ps-width optical pulses with peak power ranging from 3.6W to 17.5W, the driver-VCSEL system has over 20% electrical-to-optical power conversion efficiency. The driver can record its output current waveform with a built-in pulse monitor. The peak data from the recorded waveform is used for automatic peak current control.