Optimizing misfit dislocation glide kinetics for enhanced threading dislocation density reduction in Si1−xGex/Si(001) layers through dynamic growth rate control

Development of analytical model for strained silicon relaxation on (100) fully relaxed Si 0.8Ge 0.2 pseudo-substrates

ABSTRACTWe have investigated magneto-transport properties of differently strained Si/ Si1−xGex resonant tunneling devices. The built-in strain was either put in the Si layers, by means of a thick., relaxed Si1−xGex buffer layer, or in the Si1−xGex layers, in which case all Si1−xGex layers were grown below the critical thickness, and a Si1−xGex spacer layer with graded Ge content was used. Magnetic fields parallel to the interface have been employed to probe the in-plane dispersion in the quantum well. This is used to study the effect of band-mixing in the two strain configurations. A field perpendicular to the interface resolves some Landau level splitting. Most strikingly, however, is the similarity in the spectra with the case when the magnetic field is applied parallel to the interfaces. This indicates broadening of the levels, possibly due to scattering, and the importance of 3-dimensional band structure effects.

Low threading dislocation Ge on Si by combining deposition and etching

Epitaxial lateral overgrowth (ELO) has been used to reduce threading dislocation (TD) densities in GaN. This paper reports transmission and scanning electron microscopy studies of TDs in GaN films grown by ELO on GaN nanocolumns produced either during growth by MBE (method 1), or by self‐organised patterning on a uniform layer grown by MOCVD (method 2). In method 1, isolated nanocolumns grew without TDs, but some TDs formed when nanocolumns coalesced. Although some of these TDs extended through the overlayer, extensive lateral migration of others, depending on the dislocation type, led to dislocation annihilation, lowering the overall TD density. In method 2, a similar process of lateral migration of TDs was observed during ELO, resulting in a continuous GaN overlayer with TD densities less than 108 cm–2. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

ABSTRACTWe have studied the possibilities of reducing the threading dislocation (TD) density in GaAs on Si using free side wall growth on patterned Si substrates and/or using a soft ZnSe interlayer in combination with post growth annealing procedures. TD densities were accurately determined using large area plan view TEM and were found to be unaffected by proximity to free side walls and by the ZnSe interlayer. Post growth heat treatments led to a factor of ∼2 reduction in TD density and to bunching of dislocations throughout the thickness of the film.

3D sequential integration of CMOS transistors, which consists in stacking transistors on top of one another, has received a lot of attention in recent years. Top level transistor process temperatures have then to be drastically reduced in order to avoid any degradation of the bottom transistor performances and preserve interconnects. Selective epitaxy, which is used for the formation of the in-situ doped raised sources and drains of the top level transistor, has then to be conducted at temperatures around 500°C (i.e. 150°C to 250°C below that of conventional processes). With conventional silicon precursors such as silane (SiH4) or, to a lesser extent, disilane (Si2H6), the epitaxial growth rate of Si is not high enough at 500°C and below[1]. We present here our latest results on the epitaxy of Si, SiGe and SiGe:B layers in the 450°C to 550°C range, with a Liquid Silicon (LS) source which is benchmarked against Si2H6. Digermane (Ge2H6) and Diborane (B2H6) were used as the precursors of Germanium (Ge) and Boron (B). A 200mm Reduced-Chemical Vapor Deposition (RP-CVD) cluster tool was used for this study. A liquid precursor gas delivery system was connected to our RP-CVD chamber, with a pressure and temperature controlled bubbler used to transform our liquid silicon source into a controlled gas flow. Surface roughness was measured with Atomic Force Microscopy (AFM). X-Ray Reflectivity and X-Ray Diffraction were used to determine layer thickness and germanium content. The atomic composition of the layers was determined with Secondary Ion Mass Spectrometry (SIMS). Finally, four Point Probe (4PP) was used to measure the layer resistivity. Si layers were grown on several tens of nanometers thick SiGe marker layers on Si (001), while SiGe and SiGeB layers were grown directly on n-type Si(001). Figure 1 shows as expected an exponential increase of the Si growth rate with temperature, with a 37 kcal.mol-1 activation energy. At 550°C, 20 Torr, the Si growth rate is ten times higher with LS than with SiH4 (for a Si atomic flow ~ 9 times lower). Figure 2 shows the growth rate of SiGe at 500°C, 20 Torr, as a function of the germanium concentration (fixed Si2H6 and LS flows, variable Ge2H6 flows). We observe a slightly over linear increase of the SiGe growth rate with the Ge content for both chemistries. This increase is due to the catalysis of H desorption from the growing surface by Ge atoms. For the same growth rate, the Ge content is significantly lower with LS than with disilane, although the atomic Si flow was less than half (1.15x10-3 for LS, versus 2.50x10-3 with disilane). The sub-linear increase of the Ge content with the Ge2H6 flow was fitted with x2/(1-x) = n x F(Ge)/F(Si) relationships, with n=0.50 (LS) and 2.19 (disilane). For a given Ge2H6 flow, the SiGe growth rate was otherwise barely higher with LS than with Si2H6. Figure 3 shows an exponential increase of the SiGe growth rate with the temperature (in the 450°C–550°C range). A 10.5 kcal.mol-1 activation energy was extracted. There is also a significant Ge content decrease as temperature increases, with a -1.95%/10°C slope. These values are comparable to those obtained with a Si2H6+Ge2H6 chemistry, Ea=14.8 kcal.mol-1 and -2.25%/10°C[2]. Figure 4 shows that, at 500°C, 20 Torr, the SiGeB growth rate increases for high B2H6 mass-flows, as with other chemistries. A significant drop of the apparent Ge concentration from XRD is also noticed as the B2H6 flow increases. This is due to (i) compressive strain compensation by small Boron atoms and (ii) a drop in the atomic Ge content. Figure 5 shows a linear increase of the Boron atomic concentration with the B2H6 mass-flow (xB/(1-xB) = 4.0 x F(Ge)/(F(Si)+F(Ge)) and (ii) an atomic Ge content which is stable then goes down as the B2H6 mass-flow goes up. As expected from strain compensation, atomic Ge content from SIMS is higher than apparent Ge concentration from XRD. As the B2H6 flow increases, we observe in Figure 6 a SiGeB resistivity decrease, a stabilization at ~0.3 mOhm.cm then a re-increase as the layer becomes polycrystalline (confirmed by XRD). AFM showed that SiGe:B surfaces were rather flat, with small islands which disappeared when the B2H6 flow became high. This could be due to a lower compressive strain in high boron concentration layers. XRD profiles were however characteristics of pseudomorphic layers with a high crystalline quality. [1] J.M. Hartmann et al., Thin Solid Films 520, 3185 (2012). [2] J.M. Hartmann et al., ECS Trans. 75 (8), 281 (2016). Figure 1

Evolution of threading dislocations in MOCVD-grown GaN films on (1 1 1) Si substrates

This study reports on defect distribution and compositional homogeneity of AlxGa1−xN layers with a nominal composition x of 0.5 grown on AlN by metal organic vapor phase epitaxy. The AlN layers with a low threading dislocation density (TDD) of a few 108 cm−2 were obtained by ELO and showed periodic surface macrosteps. AlxGa1−xN growth on these AlN surfaces results in inhomogeneous Ga distribution due to enhanced Ga incorporation on the macrostep sidewalls. Variation of AlGaN deposition rate strongly influences the Ga distribution as well as the defect structure in the layers. Low growth rates (0.2 μm h−1) result in an inhomogeneous TD distribution with formation of alternating stripes with lower and higher defect densities. Additionally, self-organized formation of additional Ga-rich areas at the top edge of the steps is observed. In contrast, at a higher growth rate of 1 μm h−1 the formation of additional Ga-rich areas can be completely suppressed, but the defect density increases. This leads to an optimum growth rate to minimize the TDD.

ABSTRACTWe have made an extensive study of Si0.82Ge0.18 film relaxation on silicon on insulator (SOI) substrates having a top Si layer 40, 70, 330nm, and 10[.proportional]m thick. SiGe films were deposited with a thickness up to 1.2[.proportional]m in an ultrahigh vacuum chemical vapor deposition system at 630°C. Following growth, films were characterized by X-ray diffraction and a dislocation revealing etch. The same level of relaxation is reached for each thickness of SiGe film independent of the substrate structure. Accompanying the film relaxation is the development of a tetragonal tensile strain in the thin Si layer of the SOI substrates. This strain reached 0.22% for the 1.2[.proportional]m film on the 40nm SOI and decreases with SOI thickness. The Si thickness of the SOI substrate also effected the threading dislocation density. For 85% relaxed films the density fell from 7×106 pits/cm2 on bulk Si to 103pits/cm2 for the 40, 70, and 330nm SOI substrates. The buried amorphous layer of the SOI substrate alters the dislocation dynamics by allowing dislocation core spreading or dislocation dissociation. The reduced strain field of these dislocations reduces dislocation interactions and the pinning that results. Without the dislocation pinning, the misfit dislocations can extend longer distances yielding a greatly reduced threading dislocation density.

ABSTRACTNovel porous amorphous/crystalline superlattices were produced by the etching of mesas containing superlattices of alternating layers of Si and Si1−xGex. These layers were grown by molecular beam epitaxy on (100) Si substrates and etched in an aqueous HF:HNO3 solution. Preferential attack and amorphization of the Si1−x Gex layers was observed, leading to the formation of alternating layers of single crystal Si and porous amorphous Si1−xGex. The etchant is highly selective and it was possible to etch extremely thin (5nm) Si0.7Ge0.3 layers between 30nm Si layers. Complete conversion of the Si0.7Ge0.3 layers to the porous amorphous state was seen in lμm wide mesas. The role of composition and thickness of the Si1−xGex layers was studied. The variation in the lateral etch depths of the Si1−xGex layers in the superlattices demonstrates that lattice strain in these layers is an important factor in the selectivity of the etch process. As the thickness of the Si1−xGex layers is decreased, transport of the etchant to and the etch products from the reaction front is reduced, limiting the penetration of the etching process. The porosities of these etched Si1−xGex layers were determined to be comparable to measured values for thick etched alloy layers.

The detrimental effects of structural defects, micro-twins (MTs) and threading dislocations (TDs), on electron mobility have been investigated for InSb quantum wells (QWs) at room temperature (RT). The constants that are necessary to calculate the electron-mobility limits of these defects were determined by a least-squares-based method that has an advantage of clear representation of the analytical results in a two-dimensional space. Based on a mathematical consideration, a general method of converting electron-mobility limits into percentage impacts upon the total electron mobility was developed. Percentage-mobility-impact analyses showed that, when InSb QWs grown on on-axis (001) GaAs substrates have a TD density of 8.7 × 108 – 3.2 × 109/cm2, 21–14 and 18–45% of electron-mobility degradation are attributed to MTs and TDs, respectively, at RT. The use of 2° off-axis (001) GaAs substrates reduces MT densities in InSb QWs, resulting in a suppression of the MT mobility impact to 3–2% and a complementary slight increase of the TD mobility impact to 22–51% in the same TD density range. This considerable TD mobility limit indicates that it should be possible to improve RT electron mobility in InSb QWs grown on 2° off-axis (001) GaAs substrates, by means of reducing TD density further (< 8.7 × 108/cm2). Although the mobility impacts due to phonons in InSb QW grown on-axis and 2° off-axis (001) GaAs substrates are 54–36 and 67–42%, respectively, phonon scattering is not a single dominant scattering factor: MTs and TDs have also substantial negative impacts upon RT electron mobilities in InSb QWs.

The reduction of threading dislocation density due to their mutual interactions in GaSb thin films grown on (001) GaAs substrates by molecular beam epitaxy has been investigated. The effectiveness of several buffer layer schemes including GaSb/AlSb strained layer superlattice and buffers for threading dislocation suppression was evaluated. High‐resolution transmission electron microscopy shows that the GaSb/GaAs interface consists of a highly periodic network of 90° pure edge misfit dislocations, with an average spacing close to that for a fully relaxed system. This results in relatively low threading densities in the GaSb epilayer, despite their large lattice constant mismatch (8.2%). The threading dislocation density as a function of GaSb film thickness was determined by plan‐view transmission electron microscopy and was found to decrease with film thickness due to mutual interactions among dislocations. It was found that a strained layer superlattice of GaSb/AlSb, with each layer close to its critical thickness, is the most effective in threading density reduction.

GaN/sapphire layers have been grown by Metal Organic Vapour Phase Epitaxy (MOVPE). An amorphous silicon nitride layer is deposited using a SiH4/NH3 mixture prior to the growth of the low temperature GaN buffer layer. Such a process induces a 3D nucleation at the early beginning of the growth, resulting in a kind of maskless ELO process with random opening sizes. This produces a significant decrease of the threading dislocation (TD) density compared to the best GaN/sapphire templates. Ultra Low Dislocation density (ULD) GaN layers were obtained with TD density as low as 7×107cm−2 as measured by atomic force microscopy (AFM), cathodoluminescence and transmission electron microscopy (TEM). Time-resolved photoluminescence experiments show that the lifetime of the A free exciton is principally limited by capture onto residual donors, similar to the situation for nearly dislocation-free homoepitaxial layers.

The effect of varying threading dislocation densities on the internal quantum efficiencies (IQEs) of InGaN quantum wells (QWs), with and without intentionally created “V-pits,” is reported here. InGaN QW samples grown on GaN-on-sapphire templates with threading dislocation densities of <1 × 108 and <1 × 109 cm−2 are compared, with and without GaN/InGaN superlattice (SL) layers incorporated to intentionally open up the threading dislocation cores and form large-size “V-pits.” The formation of “V-pits” is confirmed by cross-sectional transmission electron microscopy to initiate from threading dislocations in the SL layers. The densities of the pits are confirmed by plan-view SEM to agree with the substrate threading dislocation densities. The experimental room temperature IQEs of the “V-pit” QW samples are enhanced to 15% ± 1% compared to 6% ± 2% for conventional QW samples. Both conventional and “V-pit” samples show insensitivity to the magnitude of the dislocation densities with respect to IQE performance, while the “V-pit” samples show shifts in the peak emission wavelengths compared to the conventional samples, attributed to strain modulation. This study provides additional understanding of the causes of the observed insensitivity of the IQEs to different threading dislocation densities.

We proposed a dislocation sink technology for achieving Si1−xGex multi-bridge-channel field-effect-transistor beyond 5 nm transistor design-rule that essentially needs an almost crystalline-defect-free Si1−xGex channel. A generation of a dislocation sink via H+ implantations in a strain-relaxed Si0.7Ge0.3 layer grown on a Si substrate and a following annealing almost annihilate completely misfit and threading dislocations located near the interface between a relaxed Si0.7Ge0.3 layer and a Si substrate. A real-time (continuous heating from room temperature to 600 °C) in situ high-resolution-transmission-electron-microscopy and inverse-fast-Fourier-transform image observation at 1.25 MV acceleration voltage obviously demonstrated the annihilation process between dislocation sinks and remaining misfit and threading dislocations during a thermal annealing, called the [SiI or GeI + VSi or VGe → Si1−xGex] annihilation process, where SiI, GeI, VSi, and VGe are interstitial Si, interstitial Ge, Si vacancy, and Ge vacancy, respectively. In particular, the annihilation process efficiency greatly depended on the dose of H+ implantation and annealing temperature; i.e. a maximum annihilation process efficiency achieved at 5 × 1015 atoms cm−2 and 800 °C.