Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

Power density and energy dissipation of digital IC's has become one of the main concerns during the recent years. With the increased usage of battery powered devices, ubiquitous computing, and increase in implantable biomedical applications, enhancing energy efficiency of digital systems is one of the key research areas in digital IC design. For applications with a low demand on throughput, sub-threshold digital operation is one of the promising techniques for ultra-low energy operation. Moreover, global energy minimum operating point of a digital static CMOS circuit, if exists, is in the sub-threshold regime; thus, realizing global minimum energy operation. This doctoral dissertation presents different energy efficiency enhancement methods for sub-threshold digital CMOS circuits. First, a high level sub-threshold energy model is developed for rapid characterization of digital circuits. Model accuracy is validated with measurements of a circuit that was fabricated in 0.18 µm process, and with simulations for smaller feature sized technologies. Second, this model is applied to compare the energy efficiency of synchronous and asynchronous circuits. It is shown that with a suitable external completion detection mechanism, energy efficiency of asynchronous circuits in the sub-threshold regime is better than the synchronous counterparts. Process selection to minimize energy dissipation is investigated. Moreover, it is shown that with the correct choice of process options, migrating to a smaller feature sized technology increases the energy efficiency of a circuit. Architectural modifications such as parallelism, pipelining, and folding are also explored and applied to reduce energy dissipation. Finally, a current sensing completion detection system is proposed and implemented for sub-threshold asynchronous circuits. Design flows for de-synchronization of synchronous circuits are presented for various cases with detailed explanations of sub-blocks of the completion detection system. As a proof of concept example, a self-timed cardiac event detector is implemented in a 65 nm CMOS process.

As per the International Technology Roadmap for Semiconductors (ITRS) the leakage power is growing exponentially and is the major part of total power consumption in the integrated device. With the growing impact of subthreshold and gate leakage, static leakage contributes more and more towards the power dissipation in deep submicron nano CMOS technology. To overcome this problem several techniques has been proposed. In this paper we analyses the subthreshold leakage minimization techniques in circuit level. We propose a circuit technique named “Feedback Sleeper-Stack (FS-S)” for efficient leakage reduction in digital circuits. The proposed technique is compared with available leakage reduction techniques for subthreshold power, total power, delay and PDP (Power Delay Product). Of the available techniques, three power gating techniques are considered for comparison namely, Sleeper, Forced Stacking (FS) and Sleepy Stack (SS). Nominal supply voltage of 0.9V is selected and 32nm BSIM4 Predictive Technology Models (PTM) is employed in the analysis. ELDO Mentor Graphics tool is used for net list simulation.

In deep sub-micron technologies, conventional silicon-based transistors are faced main several problems related to the short-channel effects such as power dissipation, subthreshold leakage, and drain-induced barrier lowering (DIBL). Graphene nano-ribbon field-effect transistors (GNRFETs) have become a potential contender as a substitute for traditional silicon-based transistors in next generation nano-electronic devices. They exhibit fantastic properties such as high charge carrier mobility, mean free path of electrons, faster switching, and high ION/IOFF ratio. In order to prove the competences and superiority of these types of transistors, various circuits like full adder (FA) cells, which are the main building block of computational systems must be simulated and studied. This paper presents redesigning various 1-bit FA cells such as Complementary Metal-Oxide-Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission-Gate (TG), Hybrid CMOS (HCMOS), and Transmission Function Adder (TFA) using MOS-GNRFET devices in 16nm technology node. Different HSPICE simulations are performed to obtain propagation delay, average power consumption, power-delay-product (PDP), and energy-delay-product (EDP) of FA cells and are compared with 16nm CMOS predictive technology model (PTM) at different supply voltages. The obtained results indicate that MOS-GNRFET based 1-bit FA cells have better performance than that of Si-CMOS one. The MOS-GNRFET based FA cells improve propagation delay and EDP at least 31.195% and 4.372%, respectively.

This paper presented the analysis of total power dissipation of AP-DCD algorithm using field programmable gate arrays (FPGAs). The static and dynamic power dissipation investigated using leakage current, supply voltage, effective capacitance and toggling frequency of the AP-DCD algorithm. It was found that the effective capacitance of AP-DCD algorithm was the main factor for the dynamic power dissipation and leakage current was the main factor for the static power dissipation. The total power dissipation was calculated by the addition of static and dynamic power. From the simulated calculation we found that the consumption of the dynamic power (2.1 mW) was significantly less than the static power (219.75 mW) dissipation and the total power consumption was 221.85 mW. Xilinx-Virtex-II Pro XC2VP30 device is one of the commonly used programmable fabrics, which was employed here for all the calculation.

Selective buried oxide (SELBOX) Metal‐Oxide‐Semiconductor Field‐Effect Transistor (MOSFET) structure can be used to reduce the kink effect and self‐heating problems associated with the silicon on insulator (SOI) MOSFET devices while maintaining the advantages of bulk MOSFET. In this paper, static power dissipation of SELBOX structure is investigated and compared with SOI and bulk structures. Various MOSFET structures are simulated and evaluated in terms of their static power dissipation. Only results from 90‐nm Complementary Metal Oxide Semiconductor (CMOS) technology devices are included in this paper. Simulation results using the Silvaco TCAD show that static power dissipation in SELBOX CMOS is similar to that of SOI devices but lower than that of bulk CMOS. Hence, SELBOX structure is found to produce relatively low‐static power dissipation while maintaining high operating speed and reducing self‐heating and kink effect. A mathematical model to describe the static power dissipation in the subthreshold region is also included. Statistical analysis show that the model and fabrication simulation results agree with P < .05 and correlation coefficient of 0.95.

Objectives: This paper analyses various Complementary MOS (CMOS) based XOR circuits in terms of their output voltage levels at deep subthreshold/low frequency region at 16-nm technology node and finds out the suitable XOR circuit for ultralow-power applications. Methods/Analysis: It also provides the worst case high and low output level for various XOR circuits at supply voltage 130 mV. Findings: In addition, it compares the average power dissipation that is the sum of both dynamic and leakage power dissipation (stand-by power dissipation) of XOR circuits along with the variability analysis of power dissipation in order to find the XOR circuit which is most robust and dissipate the least average power. Novelty/Improvement: Simulation result shows that Power-less XOR circuit is having a good output high and low level in all cases and most promising in terms of robustness and average power dissipation among all the other XOR circuits at deep subthreshold/ low frequency region of operation.

IntroductionThe conventional method for teaching removable partial denture (RPD) design using a pencil drawing on a solid cast has always been the basis for teaching RPD design in most dental schools at both the undergraduate and graduate levels. This does not apply to RPD fabrication technology, as more laboratories have recently adopted more efficient and versatile digital techniques to design and fabricate RPD frameworks.MethodsAt the University of Iowa College of Dentistry, we created a pilot workshop to assess the efficiency of a new approach to teaching RPD design utilizing this new digital RPD technology as a teaching tool for graduate prosthodontics residents. Three first-year prosthodontics residents were enrolled in the workshop, which involved learning the new digital workflow of designing RPD.ResultsThis new teaching approach very successfully achieved its educational goals. The residents reported that the digital RPD teaching approach enriched their knowledge and deepened their understanding of RPD design.DiscussionThe technique garnered significant interest from the students and seemed to also increase their understanding of the steps involved in RPD fabrication as well as the different components of the RPD.

In the anticipated spectrum, a lot of work has gone into managing the trade-offs between power, location, and efficiency in the moderate efficiency, moderate power region. However, research into the extremities of this spectrum remains restricted. In particular, there hasn't been enough research done on the extremes of extraordinarily low power consumption with appropriate efficiency and extraordinary efficiency with energy that is within realistic bounds. In this work, very low subthreshold power levels are used to study the power consumption characteristics of digital logic circuits in static Complementary Metal-Oxide-Semiconductor (CMOS) devices. The study shows that operating transistors below their threshold voltage might result in significant energy savings. This research emphasises the significance of subthreshold design strategies for contemporary electronic circuits that aspire for low-power operation without sacrificing efficiency. The results highlight the potential for significant progress in energy-efficient circuit design and highlight the delicate balance between preserving performance and cutting power usage. As a result, this research adds to our understanding of low-power electronics and provides information that may lead to the development of future technologies that are more efficient and sustainable. Keywords— Power consumption analysis, Digital logic circuits, Ultra-low power, Subthreshold operation, Static CMOS gates

This conference paper presents the design and implementation of a low-power 4-bit Arithmetic Logic Unit (ALU) with a Random-Access-Memory (RAM) module on Cadence platform. The proposed ALU architecture aims to address the growing demand for energy-efficient processors in modern computing systems. In this work, we leverage advanced low-power design techniques to optimize the ALU's static leakage power by around 66.24% while ensuring minimal performance degradation. The design uses minimum required transistors with power gating to reduce dynamic and static power dissipation. Power Gating is performed by shutting down the power for a portion of the design in order to reduce the static(leakage) power in the design. Furthermore, we introduce an integrated RAM module within the ALU architecture to enhance overall data handling capabilities and minimize data access latency. The RAM is carefully designed to consume minimal power during read and write operations, contributing to the overall energy efficiency of the ALU. The proposed design is simulated and validated on the Cadence platform to assess its performance and power characteristics. The simulation results demonstrate significant improvements in power efficiency compared to conventional ALUs without compromising on critical performance metrics. Moreover, the integrated RAM module showcases notable gains in data handling and access speed. In conclusion, the presented low-power 4-bit ALU design with an integrated RAM module on Cadence offers a promising solution for energy-conscious computing systems.

In the sub 70 nm technologies, the leakage power dominates dynamic power. Most of the power calculation methods account for dynamic power dissipation and static leakage power dissipation, but the runtime leakage is generally neglected. It has been shown in recent studies that the contribution of runtime leakage power to the total power dissipation is not negligible any more. The dynamic power dissipation as well as the runtime leakage power depends on the sequence in which the test vectors are fed to it. This necessitates a pre-test phase to identify the sequence of test patterns to minimize the total power. Vector reordering problem is NP-complete and effective heuristic solutions have been proposed in the past. In this paper, we present an approach based on Particle Swarm Optimization (PSO), for vector reordering. PSO is based on the iterative use of a set of particles that correspond to states in an optimization problem, moving each agent in a numerical space looking for the optimal position. Experiments on ISCAS89 benchmark circuits validate the effectiveness of our work. Our approach obtained a maximum saving of 69.75% in the total number of transitions, 45.83% in peak transition, 68.05% in dynamic power, 42.56% in peak dynamic power, 0.38% in leakage power and 59.58% in total power dissipation over unordered test set.

New complex and Low Power systems are being implemented using advanced Electronic Design Automation (EDA) tools. Low power designs are not only used in small size applications like mobile phones, tablets and handheld devices but also in high-performance computing applications. As the complexity increases day by day, the dissipation of power has emerged as one of the very important design constraints. In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. Flip-flops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption. The performance of the Flip-Flop is an important element to determine the performance of the synchronous circuit. In the research of low power and low voltage VLSI circuits, the use and implementation of Dual Edge Triggered Flip-Flop (DETFF) has gained more attention at the gate level design. The main advantage of using DETFF is that it allows one to maintain a constant throughput while operating at only half the clock frequency. In this paper, a dual-edge triggered sense amplifier flip-flop is designed for low power systems. For DETFF, the optimal delay, power consumption, and energy are determined as the primary figures of merit. The use of dual edge-triggered flip-flops can help reduce the clock frequency to half of the single edge-triggered flip-flops while maintaining the same data throughput, this thereafter translates to better performance in terms of both power dissipation and speed.

In this paper, we present a new radiation tolerant CMOS standard cell library, and demonstrate its effectiveness in implementing radiation hardened digital circuits. We exploit the fact that if a gate is implemented using only PMOS (NMOS) transistors then a radiation particle strike can result only in logic a 0 to 1 (1 to 0) flip. Based on this observation, we derive our radiation hardened gates from regular static CMOS gates. In particular, we separate the PMOS and NMOS devices, and split the gate output into two signals. One of these outputs of our radiation tolerant gate is generated using PMOS transistors, and it drives other PMOS transistors (only) in its fanout. Similarly, the other output (generated from NMOS transistors) drives only other NMOS transistors in its fanout. Now, if a radiation particle strikes one of the outputs of the radiation tolerant gate, then the gates in the fanout enter a high-impedance state, and hence preserve their output values. Our radiation hardened gates exhibit an extremely high degree of SEU tolerance, which is validated at the circuit level. Using these gates, we also implement circuit level hardening based on logical masking, to selectively harden those gates in a circuit which contribute most to the soft error failure of the circuit. The gates with a low probability of logical masking are replaced by SEU tolerant gates from our new library, such that the digital design achieves a 90% soft error rate reduction. Experimental results demonstrate that this reduction is achieved with a modest layout area and delay penalty of 62% and 29% respectively, for area mapped designs. In contrast with existing approaches, our approach results in SEU immunity for extremely large critical charge values (>650fC).

Complementary metal oxide semiconductor (CMOS) is a low-power technology typically used in the efficient implementation of digital circuits. However, at nanodimensions, CMOS has problems due to its short channel effects and subthreshold leakage currents. These drawbacks can be overcome with quantum-dot cellular automata (QCA) which is one of the fastest nanotechnologies operated at THz rate. Thus, all digital circuits can now be implemented by QCA at the required nanoscale. This paper proposes a novel, energy-efficient and area-optimized 1-bit full adder design using QCA which provides efficient clocking, reduced cell count and reduced energy dissipation. The proposed design utilizes only 26 quantum cells in 0.02 µm2 area and has a reduction of 8% in number of cells, 75% in delay and 4% in energy dissipation at 1 K compared to the existing works. This innovative full adder design is used to implement a 4 × 4 Baugh–Wooley multiplier. The simulation results of the multiplier observed on QCADesigner 2.0.3 tool validate that the Baugh–Wooley multiplier designed with the novel 1-bit full adder yields better performance in terms of 9% reduction in area, 17.4% reduction in quantum cells used and reduced power dissipation of 2.44nW.

In recent years, reversible logic has emerged as a major area of research due to its ability to reduce the power dissipation, which is the main requirement in the low-power digital circuit design. It has wide applications such as low-power CMOS design, nanotechnology, digital signal processing, communication, DNA computing, and optical computing. In this paper, two new 3 × 3 reversible gates are proposed and these are being used to realize the classical set of logic gates in the reversible domain. An important aspect of the two newly proposed reversible gates is that a novel optimized 1-bit comparator can be realized. The proposed reversible 1-bit comparator is better and optimized in terms of the number of reversible gates used, the number of transistor counts, and the number of garbage outputs. Also, a 4-bit comparator has been designed by cascading 1-bit comparators in series. Using this, a 32-bit reversible comparator has been proposed. Proposed circuits have been simulated using Modelsim.KeywordsReversible comparatorReversible logicFPGA

The performance of Static Nanomaterials Random-Access Memories (SRAMs) is often degraded in the sub-threshold region as it is susceptible to increased access energy and leakage power. However, the low-power operation of SRAM is very much essential for efficient device functioning. Accordingly, designing robust SRAM cells that maintain stability and minimize power consumption is a key challenge. In this regard, with this ongoing work, the authors present novel designs of SRAMs using memristor technology by mitigating the shortcomings discussed above. This paper proposes a novel SRAM architecture of four transistors and five memristors, by integrating memristor technology to achieve drastic improvement in performance at subthreshold regions. Further, it performs an analysis of the metrics of static noise margin and power consumption to comprehensively evaluate the proposed SRAM designs. Simulation using Cadence Virtuoso for 65 nm technology demonstrates that power consumption for a 4T5M cell is about two and a half times lower than for 4T4M and 1.2 times lower than for 4T3M, hence proving that it will be promising for extremely low-power applications.