Performance driven BIST technique for random logic

In this paper, a heuristic method based on a pre-calculated prediction of tests is presented. This method is for combinational test generation and applies to the combinational parts of sequential circuits equally wells. The proposed method is Directed Random Test Generation that is based on SCOAP observability and controllability parameters. RTG methods are usually evaluated based on fault coverage that grows exponentially with the number of test vectors. Instead of pure random testing with a massive number of test vectors, fewer test vectors are selected by Directed Random Test Generation, and more faults are detected in the early stages of test generation. As a result, fewer faults remain for the deterministic test stage, which is helpful where online testing is considered. A comparison between random testing and directed random testing is performed on combinational benchmarks, using MATLAB and ModelSim simulation environments. The focus is on the stuck-at fault models in random logic circuits. The simulation results show our method has a sharper increase in fault coverage when compared with pure random test generation.

Chapter 1 - The History of Plasma Processing

BELLMAC-32A is a single-chip fully 32-bit high-end microprocessor designed in 2.5-?m twin-tub CMOS technology. This paper describes the gate matrix layout of random control logic in BELLMAC-32A with top-down hierarchical design methodology. The gate matrix layout provided (1) parallel team layout efforts, (2) adaptability to evolving logic design with short turnaround time, (3) high packing density competitive with hand layout, (4) compatibility with computer-aided layout and verification tools, (5) capability to fine-tune circuits, and (6) technology updatability. It took 6.5 engineer-years to complete the layout of random control logic with 7000 transistors although the logic design was continuously evolving during the layout period. The average packing density of gate matrix layout was 1500 ?m2 per transistor in random logic and 840 ?m2 per transistor in data path. BELLMAC-32A had more-than-three times performance improvement over its 3.5 ?m technology prototype chip BELLMAC-32, in which random control logic was implemented with polycells.

Data path circuits are regular and best placed in bit-sliced pattern for improved Quality of Results such as timing, power, congestion and area. The cells in a column of bit slice structure are normally aligned on control pins or clock pins for straight routes, reducing power. The traditional way of placing data path circuits, using separate data path placer and then bringing them as macro in main design has its significant disadvantages. It is important for modern day placement tool to place random logic and data path circuits concurrently respecting the regularity that a data path circuit has by placing them in bit-sliced manner. It is not only important to place the data path elements in bit-sliced pattern but also that structure has to be maintained throughout the flow. The different set of optimization tricks can be applied to different bits of data path which can destroy the identical footprints of cells in column and that brings challenge of maintaining pin alignment. In addition to that, in lower nanometer nodes, fixed physical only cells pre-placed throughout the core area pose challenge of keeping bit-sliced structure intact. A flow for handling data path circuits in a place and route tool along with an algorithm for bit slice tiling is being proposed in this paper which addresses the challenges mentioned above.

Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead.

This paper presents a novel design methodology to turn the timing violation caused by aging into computation approximation error without the reliability guardband or increasing the supply voltage. It can be realized by accurately monitoring the critical path delay at run-time. We evaluate the proposal at two levels: RTL component level and system level. The experimental results at the RTL component level show a significant improvement in terms of (normalized) mean squared error caused by timing violation, and those at the system level show that the proposed approach successfully transforms the aging-induced timing violation errors into much less harmful computation approximation errors, and thus it recovers image quality up to perceptually acceptable levels. It reduces the dynamic and static power consumptions by 21.45% and 10.78%, respectively, with 0.8% area overhead compared to the conventional approach.

Area-efficient high-coverage LBIST

The advancement of semiconductor technology has driven the continuous reduction in transistor sizes, resulting in significant improvements in both area efficiency and power consumption. However, these advancements have also increased susceptibility to faults caused by energetic particles. Triple modular redundancy (TMR) is a well-known logical masking technique that employs three copies of a given circuit alongside majority voters, guaranteeing 100\% single-fault coverage in the replicated modules. This reliability, however, comes at the cost of over 200\% area overhead. The approximate TMR (ATMR) concept leverages non-exact module functionality to reduce the associated area overhead while accepting a reduction in fault coverage. This work provides a comprehensive survey of ATMR generation techniques, detailing the various approximation strategies and discussing the primary approximation control mechanisms. Additionally, it presents a comparative analysis of the surveyed works, focusing on scalability and the trade-offs between area overhead and fault coverage achieved by the generated ATMR designs.

Due to increasing integrated circuit design complexity, engineering change orders (ECOs) have become a necessary technique to resolve late-found functional errors and/or performance deficiencies. To fix timing violations, gate sizing and buffer insertion are commonly used in postmask ECO. These techniques, however, may not be powerful enough, especially when spare cells are inserted to balance between functional and timing repair capabilities. We propose a postmask ECO technique, called TRECO, to remedy timing violations based on technology remapping, which also supports functional ECO. Unlike conventional technology mapping, TRECO performs technology mapping with respect to a limited set of spare cells and confronts dynamic changes of wiring cost incurred by selection of different spare cells. With a precomputed lookup table of representative circuit templates, TRECO iteratively performs technology remapping to restructure timing critical subcircuits until no timing violation can be further removed. Experimental results on five industrial designs show the effectiveness of TRECO in ECO timing optimization and in timing-aware functional ECO.

Test Generation for asynchronous circuit is a hard problem mainly due to the absence of a global clock. Full scan design based test generation of asynchronous circuits seems to be feasible but at an expense of large area overhead. Partial scan should be a better option with lower area overhead but there is no known systematic way of selecting which asynchronous state-holding elements to scan. This paper presents a partial scan and automatic test generation methodology based on a novel adaptation of BALLAST for asynchronous circuits and time frame unrolling. Balanced structures are used to guide the selection of the state-holding elements that will be scanned. A cyclic to acyclic conversion of the input circuit is used to create a combinational circuit for which test patterns are easily generated using well known methods. These test patterns are then used to test the original circuit. Fault coverage and area overhead results of this method are obtained and analyzed with full scan and other methods.

We propose a novel FIR filter architecture that mitigates sub-critical timing violations as they occur in the pipeline structure by momentarily bypassing affected coefficients. Timing violations are detected using known in situ circuit-level techniques based on late transition detection at timing end points. The approach enables operation with a small but non-zero logical error rate, such that process, voltage and temperature margins can be eliminated without compromising stop-band attenuation. The proposed architecture is implemented in a 90nm CMOS process technology using a typical commercial standard cell implementation flow and verified using full model SPICE simulations. The filter operates at a maximum clock frequency of 420 MHz at 1 V, with an estimated area and power overhead of 26% and 24% respectively compared to a conventional implementation. At the typical process and temperature corner, the proposed architecture can be scaled in voltage down to the point of first failure at 730 mV, thereby achieving a 53% power saving, with no detectable degradation in stop-band attenuation characteristics.

The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-end processors can use elaborate techniques like multiple issue, out-of-order execution, speculative execution, value prediction etc. to tolerate high memory latencies, they are often not viable solutions for embedded processors, due to significant area, power and chip complexity overheads. This paper proposes a hardware-software cooperative approach, called priority-based execution to hide cache miss penalty for embedded processors. The compiler classifies the instructions into low-priority and high-priority instructions. The processor executes the high-priority instructions, but delays the execution of low priority instructions. They are executed on a cache miss to hide the cache miss penalty. We empirically evaluate our proposal on the Intel XScale compiler and microarchitecture. Experimental results on benchmarks from Multimedia, MediaBench, MiBench, and SPEC2000 demonstrate an average 17% performance improvements, hiding 75% cache miss penalty.

Effect of the catalyst wettability on the performance of a trickle-bed reactor for ethanol oxidation as a case study

This paper focuses on realization of high per- formance motion control based on acceleration control. A high sampling frequency is known to be effective for improving the performance. Characteristics of acceleration control are investigated and the relationship between the performance and the sampling frequency of the system is discussed. Based on these considerations, a new multirate sampling method for the acceleration control system is proposed. Disturbance observer is redesigned for application in the multirate system. Stability analysis is performed to verify the validity of the proposal. Feasibility of the proposal and influence on the performance are also verified by experimental results. frequency of acceleration control. The needs of a higher sampling frequency for output than for input are de- scribed. From this point of view, this paper proposes a new multirate sampling method with a shorter output sampling period for improvement of acceleration control performance. Disturbance observer is redesigned to fit to the multirate system with a new definition of dis- turbance torque. Stability analysis is performed to make a comparison with single-rate control and to verify the validity of the proposal. Experimental results support the feasibility of the proposed method and improvement of the performance. This study considers the system in the 1st dimension for simplicity.

ABSTRACTDevelopment of the separation equation in a classical Clusius-Dickel column with sidestream operations for the heavy water enrichment has been accomplished theoretically. Performance of the modified Clusius-Dickel column with sidestream operations and its corresponding maximum separation was determined with the sidestream flow-rate ratio at the feed position and top flow-rate fraction as parameters. The effect of the sidestream operation of a modified Clusius-Dickel column on separation efficiencies for the H2O-HDO-D2O system has been investigated theoretically and experimentally. The theoretical predictions were in good agreement with the experimental results. The theoretical results indicated that the maximum separation efficiency increases with the side stream flow-rate fraction but decreases with feed flow rate and are represented graphically and compared with that in a classical Clusius-Dickel column. Considerable improvement in the device performance is obtained by employing a modified Clusius-Dickel column under sidestream operations and flow-rate fraction variations, instead of using a classical Clusius-Dickel column.