Polar codes for NAND-based SSD systems: A joint source channel coding perspective

Turbo Codes and Tail Biting Convolutional Codes are used for channel coding in LTE, but these codes are not pertinent in 5G. For Channel coding, advanced error correction techniques are required for the 5G. Polar codes are adopted for control information and LDPC codes are required for Data information for the 5G. Various coding techniques such as LDPC codes, Quasi Cyclic (QC)-LDPC codes, Non-Binary (NB)-LDPC codes, Spatially Coupled (SC)-LDPC codes, Irregular Repeat Accumulate (IRA) codes, Polar codes, Distributed CRC Aided (DCA) codes, and Fountain codes are illustrated. For Decoding Min-Sum Algorithm and Belief Propagation are used for LDPC codes. Min-Sum, OMS, NMS, BP methods are applied in QC-LDPC codes. SC, SCL, FSCL, CASCL, BP algorithms implemented for Polar codes. Simulation of QC-LDPC codes, Polar codes, and LDPC codes are generated by using MATLAB Software. The performance of all channel coding techniques with consideration to BER and BLER is mentioned.

Polar codes were shown to be weak at finite block lengths even under maximum-likelihood (ML) decoding. To enhance polar codes, CRC-aided polar codes were proposed. It has been shown that CRC-aided polar codes under the successive cancellation list (SCL) decoder outperform LDPC codes and turbo codes. Recently, interleaved polar (i-polar) codes were proposed. By using a new bit channel selection algorithm, i-polar codes without CRC were shown to outperform the 5G LDPC codes. However, most research on polar codes focuses on the binary case. In this paper, a new family of nonbinary i-polar codes with random constellation mapping is proposed. A recursive form for calculating the average weight enumerating function (WEF) of the nonbinary i-polar code is derived. With the random constellation mapping, the upper bound on the BLER under ML decoding depends on the WEF of the nonbinary i-polar code. Then a new channel selection algorithm is proposed based on the polarization effect and the BLER upper bound. The algorithm generates a sequence, termed the i-polar sequence (IPS). Simulation results show that the nonbinary i-polar codes with the IPS outperform the 5G LDPC codes.

In this paper, we study two problems of providing reliable data transmission and developing aggregation techniques for correlated data in wireless sensor networks. A system with forward error correction (FEC) can provide an objective reliability while using less transmission power than a system without FEC. Because of the additional parity bits and encoding/decoding energy consumptions, we study the effect of FEC on energy efficiency. We propose to use LDPC codes for FEC. We show that wireless sensor networks using LDPC codes are almost 45% more energy efficient than those that use BCH codes, which were shown to be 15% more energy efficient than the best performing convolutional codes. Then we study the problem of providing aggregation for two and three correlated nodes in wireless sensor networks. We propose to use LDPC codes in wireless sensor networks for source and channel coding to obtain a two-fold energy savings. For two correlated nodes, we study both distributed source coding and joint source-channel coding. While distributed source coding using LDPC codes was studied before, joint source-channel coding using LDPC codes is introduced for the first time. The difference between our work in distributed source coding using LDPC codes and the previous work lies in the LDPC code design procedure. The simulation results show that our proposed design criteria improves the performance of the source coding. The convergence of the non-uniform LDPC code of our design technique is almost 60% closer to the Slepian-Wolf limit. For three correlated nodes, we study distributed source coding using LDPC codes. We simplified the problem of design procedure to randomly punctured LDPC codes. This is a new approach for designing LDPC codes and the simulation results for code of length 1000 shows that the convergence of the LDPC code is achieved at compression rate 0.3174 which is only 0.08 away from the Slepian-Wolf limit.

Both polar code and Low-Density Parity-Check (LDPC) code have been adopted in 3GPP eMBB scenario. Some scholars have proposed a serial concatenation structure combining these two codes. However, the inner code needs to add redundant bits to protect the redundant bits of the outer code in the serial concatenation. In this paper, we propose a parallel concatenation code combining polar code and LDPC code on the AWGN channel, which does not distinguish the inner code from the outer code. In the proposed concatenated structure, the BP algorithm is used to decode polar code, and the output soft information of BP decoder is logarithmically processed before LDPC decoding. According to the simulation results, compared with the serial concatenated code with the same code rate and code length, the parallel concatenated code has better BER(Bit-Error-Rate) performance.

Turbo codes are attractive compared with Low Density Parity Check (LDPC) codes for Forward Error Correction (FEC) applications mainly due to their superior performance, especially at low Signal-to-Noise Ratio (SNR) such as are common in Powerline channels. For example, IEEE 1901-FFT PHY used the Turbo coding scheme defined in the HomePlug AV standards. However, patent fees are usually required for each turbo-code enabled manufactured device. The objective of this paper is to examine whether unlicensed LDPC codes, with optimized choices of block lengths, could be a viable alternative for future Powerline Communications (PLC) applications. The paper shows that the performance of the LDPC codes can approximate that of the Turbo codes with higher block lengths, on channels with typical and realistic PLC characteristics. The paper also shows that the additional complexity associated with this increase in block length can be mitigated by the use of Quasi-Cyclic LDPC (QC-LDPC) codes.

Error control coding improves reliability and efficiency of wireless communication systems. This research delves into the latest advancements in error control coding schemes for wireless communication systems, with a specific focus on their application within the domain of Low Power Wide Area Networks (LPWANs) such as Narrowband Internet of Things (NB-IoT) systems, LoRa energy-efficient hardware design, random access control systems, and wireless sensor networks. In the context of LPWANs, particularly NB-IoT systems, we investigate the adaptive coding and modulation (ACM) in NB-IoT systems, which adapts coding rates and modulation techniques to changing channel circumstances. Comprehensive analysis of the literature review shows that the proposed approaches are more energy efficient and less error-prone than fixed coding and modulation schemes. Using Cell Design Methodology (CDM), Single Error Correction (SEC) codes are optimized for energy efficiency. Power and energy efficiency have improved in standard CMOS and CDM logic systems. This impacts IoT devices, memory storage, and security systems. Next, Forward Error Correction (FEC) is examined for ALOHA-based random-access control systems wherein packet loss rate and spectral efficiency metrics are mathematically calculated. FEC is beneficial, especially when time and frequency synchronization diverge. Monte Carlo simulations studied in the literature shows that FEC improves satellite communication systems. This review establishes benefits of FEC, notably in satellite communications systems. In addition, Wireless Sensor Networks (WSNs) error control techniques and network reliability and performance are examined along with Convolutional, Turbo, Low density parity check codes(LDPC), and Polar error correction coding (ECC) methods. We learn about their benefits, drawbacks, and implementation challenges by assessing their efficacy, efficiency, and applicability in wireless sensor networks (WSN) applications. This study further highlights advancements of energy-efficient error control coding when, integrated into network designs alongwith the trade-offs between efficacy and intricacy to help improve wireless communication networks. Finally, this study summarizes current error control coding approaches for wireless communication systems. We provide insights into improving reliability, energy conservation, and efficacy by examining ACM, CDM, FEC, and error correction coding (ECC) across varied domains including LPWAN and IoT technologies with earnest hope to facilitate researchers, engineers, and professionals working in the field of error control coding in wireless communication.

In this paper, polar codes, low-density parity-check (LDPC) codes and convolutional codes in the status of high-performance wireless (WirelessHP) are discussed. Those classic code schemes are compared in terms of their encoding and decoding complexity and the error-correcting performance. Results show that, polar codes with successive cancellation list (SCL) decoding is superior to the LDPC codes and the convolutional codes in the condition of WirelessHP. The result has certain significance for the development of next generation communication technology.

Error-correction codes (ECC) or channel codes allow correcting errors in a data sequence without the need to refer to the original source of information. By allowing reliable data transmission and storage despite the inevitable noise that perturbs physical signals, they dramatically reduce the cost of computer systems, and as such play a central role in enabling the digital revolution that we witness today. However, the decoding of channel codes often represents a significant part of the latency and energy consumption of a receiver. In this chapter, we review methods that can reduce the implementation complexity of ECC decoders by relying on stochastic computing. We focus on an important type of code called low-density parity-check (LDPC) codes, which are capacity-approaching codes that can be decoded using message-passing algorithms. These algorithms are inherently parallel, making LDPC codes attractive for simultaneously achieving a large coding gain and a high data throughput. In addition, we show that the use of stochastic computing is not limited to binary LDPC codes by describing a stochastic-computing decoder for non-binary LDPC codes, and another for Turbo codes.

<div> <h2>Abstract</h2> <p><strong>Objective:</strong> In the code theory, parallel concatenation of codes becomes more popular after the introduction of turbo codes. In recent years, the Low Density Parity Check (LDPC) code has found remarkable advancement and has seen them outshine turbo codes in terms of performance especially in the error floor and higher code rate. The main objective of this paper is to address the various techniques of a parallel concatenation of LDPC code in code theory. <strong>Method/Finding:</strong> To reduce the complexity of encoding and decoding for longer codes various parallel concatenation of LDPC coding methods were introduced and the performance was compared with other work. <strong>Novelty:</strong> When a longer block length is used, the parallel LDPC decoder is suffered from the complexity of prohibitive implementation. To overcome this issue and to achieve the best performance for longer codes, the different methods for parallel concatenation of LDPC codes were introduced with reduced complexity. This will helps to break the long and complex LDPC code into less complex and smaller LDPC to distribute the decoding and encoding load. Also, this will provides scalability and scope for improving the performance of LDPC codes in practical delay-sensitive and energy-aware applications.</p> <p><strong>Keywords:</strong> Parallel concatenation; LowDensity ParityCheck (LDPC); turbo codes; Parallel Concatenated Gallager Codes (PCGC)</p> </div> <div></div> <div> </div>

The increasing demand for high-density and high-speed digital optical recording systems has made the development of advanced coding and signal processing techniques for fast and reliable data recovery increasingly important. In recent years, the parity-check (PC)-code-based reception technique has been widely studied for magnetic recording systems, and it is projected to be highly promising for high-density optical recording. The PC code is an inner error correction code (ECC), which can detect dominant short error events of the system, using only a few parity bits. This reduces the loss in error correction capability of the outer ECC due to random short errors and results in a simple and efficient solution to improve the overall performance. This thesis is dedicated to the design and analysis of PCcode- based recording systems to achieve higher recording capacity with low implementation complexity, for high-density blue laser disc systems. In particular, most of the key components of the PC-code-based optical recording system have been designed and optimized for different recording densities, and different proportions of white noise and media noise. During the development of advanced coding and detection techniques, it becomes necessary to investigate the system’s performance with different coding schemes and recording densities. In Chapter 2 of the thesis, we propose a generalized Braat-Hopkins model for optical recording channels, which provides a fair basis for the performance comparison of detection schemes over different coding schemes and recording densities, for channels with additive, white Gaussian noise (AWGN) and media noise. Various basic issues associated with the PC-code-based systems are investigated in Chapter 3. These include bounds for bit error rates and error event probabilities, the dominant error events at channel detector output, different PC codes, simple and efficient post-processors, the impact of error events that are split across data block boundaries and the corresponding remedy, as well as the effects of code rates and recording densities. Simulation results show that a 4-bit PC code achieves the best performance. The corresponding bit error rates (BERs) are very close to the performance bounds, at both nominal and high densities. Constrained codes, which serve as a key component in the read-write channel of data storage systems, are desired to have a high code rate with low-complexity encoder/decoder. In Chapter 4, we investigate the design of certain capacity-approaching constrained codes for optical recording systems. In particular, we derive analytically the relationship between the number of encoder states and the maximum size of these codes. We identify the minimum number of encoder states that maximizes the code rate, for any desired codeword length. The design of constrained PC codes is key to the development of PCcode- based systems, and the systematic design of efficient constrained PC codes remains a challenging problem. In Chapter 5, we propose a general and systematic code design technique for constructing capacity-approaching constrained PC codes, which can detect any type of error events of the system, with the minimum code rate loss. Compared to the rate 2/3 code without parity, the newly designed constrained 4-bit PC code achieves a performance gain of 2 dB at nominal density, and 1.5 dB at high density, at BER = 10-5. As the dominant noise for high-density optical recording systems, media noise severely degrades the performance of channel detectors and postprocessors that are designed for AWGN. In Chapter 6, we propose two novel modifications to the bit detector to combat media noise. We further develop a data-dependent post-processing scheme for error correction. Compared to the system designed without considering media noise and without PC codes, the overall performance gain of the developed scheme can be more than 11 dB at high media noise levels. In data storage systems, the ECC failure rate (EFR) serves as the ultimate measure of the data recovery performance. In Chapter 7, we develop semi-analytical approaches for estimating the EFR, and analyze EFRs for the developed PC-code-based systems, for the cases without and with interleaving. Our analysis shows that with the optimum interleaving degrees, compared to the rate 9/13 code without parity, the 2-bit PC code achieves a gain of around 0.5 dB, and the 4-bit PC code gains 0.6 dB, at high record ing density and EFR = 10-16. The thesis concludes in Chapter 8 with some suggestions for further work.

Turbo and LDPC (low-density parity check) codes are simple and new types of error correction codes which give a powerful and practical performance of error correction. Although experimental results show their efficacy, further theoretical analysis is necessary, which is not straightforward. We have built a unified framework of turbo and LDPC codes based on information geometry. The framework helps our intuitive understanding of the codes and opens a new prospect of further analysis. We have revealed some properties of these codes in the proposed framework. This paper summarizes the results.

Polar code has been proven to obtain Shannon capacity for Binary Input Discrete Memoryless Channel (BIDMC) and its use has been proposed as the channel coding in 5G technology. However, its performance is limited in finite block length, compared to Turbo or LDPC codes. This research proposes the use of various CRC codes to complement Polar codes with finite block length and analyses the performance based on Block Error Rate (BLER) to Es/N0 (dB). The CRC codes used are of degrees 11 and 24, with 3 different polynomial generators for each degree. The number of bits in the information sequence is 32. The list sizes used are 1, 2, 4, and 8. Simulation results show that the concatenation of CRC and Polar codes will yield good BLER vs Es/N0 performance for short blocks of codeword, with rates 32/864 and 54/864. Concatenating CRC codes with Polar codes will yield a BLER performance of 10-2 with Es/N0 values of -9.1 to -7.5 dB when CRC codes of degree 11 is used, depending on the SC list used. The use of CRC codes of degree 24 enables a BLER performance of 10-2 with Es/N0 values of -7 to -6 dB when the SC list used is 1 or 2. The use of CRC codes of degree 24 combined with SC list with sizes 4 or 8 will improve the BLER performance to 10-2 with Es/N0 values of -8 to -7.5 dB

Interleaver module is an important part of modern mobile communication system. It plays an important role in reducing bit error rate and improving transmission efficiency over fading channels. In 5G NR (5th Generation New Radio) standards, LDPC (low-density parity-check) and polar channel codes are employed for data channels and control channels, respectively. If multiple interleavers are implemented separately for them, the cost increases significantly. To address this issue, a hardware multiplexing scheme for channel interleavers based on LDPC and polar codes is proposed in this paper. Firstly, the formulas for the processes of the control channel interleaving and data channel interleaving are derived with respect to 5G NR standard. Then, the hardware implementation structures of the two interleavers are given. Subsequently, hardware reuse is proposed by sharing the similar or identical parts between the two hardware structures. Simulation results verify the correctness of our proposed scheme and demonstrate that it can realize the hardware sharing of the two kinds of channel interleavers to reduce the cost of silicon.

Low Density Parity Check (LDPC) codes are Shannon-Limit approaching codes. Shannon stated the theoretical bounds for digital data transmission in a given channel capacity with error correction coding. Spread Spectrum also called as CDMA (Code Division Multiple Access) is an efficient way of radio wave communication deployed in commercial broadcasts, ham radios, military communications, police radios, etc. CDMA is a means of signal transmission in which the signal frequency is spread over a very wide bandwidth. Spreading of data is achieved prior to transmission with the help of an independent code called ‘Pseudo Noise Code’ (PN sequences), which is subsequently used in the receiver end to de-spread the signal received in order to recover the signal data. PN sequences based on prime numbers like Legendre & Weil sequences are used in the present work. An impressive part of LDPC lies in its decoding algorithm. Sum-Product Algorithm (SPA) decoding offers the best error performance amongst all the types of decoding techniques of LDPC codes and thus applied here. This paper demonstrates an idea of introducing LDPC codes along with DS-Spread Spectrum technique using Legendre & Weil sequences. In the present work, the encoding and decoding algorithms are applied after spreading of the signal. SPA decoding technique is successfully employed and simulated results are plotted taking an example design to illustrate the concepts discussed above.

In communication systems, the transmitted data is corrupted by channel perturbations, such as noise and fading, which affect the reliability of the received data. Error correction codes are employed to mitigate channel perturbations. However, design and implementation of good and efficient error correction codes remains an open problem. In this paper, Low Density Parity Check (LDPC) codes are considered as they provide a reasonable trade-off between computational complexity and reliability. Good LDPC codes should ideally provide low complexity, close to capacity acheivable transmission rate, high coding threshold, and high decoding stability. In this paper, we investigate a joint LDPC code optimization algorithm using Genetic Algorithm (GA) and Linear Programming (LP) to determine the variable nodes and check nodes degrees distributions. EXIT chart analysis and Frame Error Rate (FER) performance are used to validate the proposed method.