Power factor corrector with adaptive digital peak current mode control

The purpose of this paper is to discuss performance characteristic of digital peak current mode control switching power supply. The proposed method can capture the peak current value in real time by using the voltage controlled oscillator (VCO), the programmable delay circuit and the signal frequency detector. Its transfer function is derived analytically. Also, the frequency characteristics are revealed using the loop transfer function in the case of different voltage control loop gains. In addition, its gain margin and phase margin are discussed. Furthermore, the transient responses of proposed method are compared with the conventional voltage mode control in the simulation and the experiment.

The boost type dc-dc converter is used for compensation of dc bus voltage in the dc power feeding system such as the renewable energy system. It should be operated stably to improve reliability of the system. The peak current mode control is applied to operate stably because the boost type dc-dc converter tends to be unstable. However, a peak value of reactor current cannot be captured in the digital controller. In this paper, a digital peak current mode control boost converter with conversion from current to frequency and using a frequency detector for a peak current detection in real time is presented. The effectiveness of the proposed method is verified by the comparison of the transient response under changing an input voltage between the conventional PID control and the proposed method.

The purpose of this paper is to present a novel digital control boundary current mode ac-dc converter. The ac-dc converter is widely used as power factor correction. The ac-dc converter that operates in a boundary current mode has the some advantages. It has capability to achieve low current distortion. The unity power factor is theoretically obtained by the boundary current mode control. In the proposed method, nonlinear equations is solved using Newton's method to predict the zero-cross point of the inductor current.

In this paper, a series-capacitor-based interleaving buck power factor correction (PFC) converter is proposed, the intermediate energy storage capacitance of which is operated at discontinuous capacitor voltage mode (DCVM), and automatic power factor (PF) correction for this converter is obtained. Moreover, the voltage across the series capacitor of the proposed PFC converter is clamped at the input voltage, and thus peak voltage stress existed in the traditional DCVM buck PFC could be relieved. By effectively regulating the charge/discharge time for the series capacitor, ultrahigh step-down conversion ratio of the proposed converter is achieved, the conversion ratio of which is independent of the duty cycle and only related to the switching frequency and circuit parameters. Therefore, high PF can be obtained due to very narrow deadtime of the input current. Meanwhile, the proposed PFC converter can realize the soft turn- on of part power switch and soft turn- off of part power diodes. In addition, comparing with the traditional discontinuous inductor current mode PFC, the input current of the proposed PFC converter is continuous so that the peak value and root-mean-square value of input current can be reduced. The operational principle, performance analysis, and parameter design principle are given in this paper. The analysis results show that the PF and total harmonic distortion are also independent of the duty cycle. Finally, a 220-Vac input, 60 W/15 V output experimental prototype is built to verify the validity of the theoretical analysis.

A digital adaptive current controller for implementation on a three-phase voltage source inverter is proposed for a demonstration 40 kVA dynamic power filter (DPF). The digital dynamic compensator controller is based on a TMS320E15 digital signal processor (DSP), which will be implemented in a hybrid power compensator of +or-100 kVA power rating. The hybrid power compensator consists of a three-phase thyristor controlled reactive (TCR) source, combined with the three-phase 40 kVA voltage-fed system. The characteristics of the digital current controller for the DPF are introduced and described. Simulation results of this digital control technique on a single-phase DPF are shown and compared with practical results obtained from a low-power (+or-300 VA) single-phase DPF. >

An adaptive control technique for a digital current mode control of dc-dc converters is proposed in this paper. The adaptive digital controller is designed to maintain the optimum gain-phase of the outer control loop regardless of the changes in the load value. In the control algorithm, the load resistance is calculated using the average current and output voltage values inside the digital processor. Next the calculated value of the load resistance is used to tune the Proportional-Integral (PI) controller such that the requirements for crossover frequency and phase margin values are fulfilled. In order to avoid the calculation burden to slow down the program execution speed, the parameter values of PI controller for each value of the load resistance are inserted into a look-up table inside the digital processor. To verify the proposed technique, the controller is implemented in an FPGA to control a buck converter. The experimental results show the excellent performance of the controller in presence of a load change.

A novel fully digital FPGA-based current controller for switched reluctance machines is presented in this paper. The digital current controller provides PWM and hysteresis band modulation in a seamless way and allows complex rotor position based shaping of the phase currents to optimize torque ripple and acoustic behavior. Arbitrary phase current waveforms can be stored in a position-addressed memory. The FPGA based implementation ensures flexible scaling and adaptation to various machine designs and inverter topologies. Experimental results prove the feasibility and performance of the chosen approach.

In this paper, we propose three advanced digital predictive current-mode control (DPCC) algorithms based on a simplified estimation method of duty cycle lost time for asymmetric half-bridge (AHB) LED constant-current driver. They are the digital predictive peak current mode control(DPPCC) algorithm based on leading-edge modulation, the digital predictive quasi-valley current mode control(DPqVCC) algorithm based on trailing-edge modulation, and the digital predictive quasi-average current mode control(DPqACC) algorithm based on double-edge modulation. Simulation and experimental results demonstrate that the three DPCC algorithms can effectively offset the effect of delay on digital control performance, which confirms the superiority of DPqACC. When the DPqACC is applied, the series-load-jump transition times are below 4.5 ms, the maximum load adjustment rate is 0.5%/ V, and the output current can be tuned continuously between 0.3 A and 4.5 A with the longest transition time of 1 ms. Moreover, the three DPCC algorithms are capable of compensating for low-frequency ripples due to the rapid regulation speed of the inner loop. With the electrolytic capacitance removed without additional ripple compensation, the maximum peak-to-peak value of the low-frequency secondary ripple is 0.1163 A (2.91%) when the input is 400 53sin(2ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>lin</i></sub> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> ) V and the output is 4 A. This approach provides an excellent solution for the digital design of low-ripple AC-DC LED constant-current drivers without electrolytic capacitance.

This paper proposes a digital control system, based on the Steinmetz method and instantaneous power theory, applied to the static var compensator to compensate the unbalance between the phases and the power factor of loads. The proposal incorporates an additional digital filtering system for elimination of harmonic components and for the extraction of positive-sequence voltage. The experimental results demonstrated good precision in the compensation of the unbalance and in the correction of the power factor. The experimental tests indicate reduction of the unbalance factor of 44.9% to 3.3% and correction of the fundamental power factor to the unit.

Improving of power factor and reducing harmonic distortion in electrical instruments are needed. An interleave boost converter is used for an active PFC (Power Factor Correction). In the interleave PFC boost converter, if a duty ratio, a load resistance and an input voltage are changed, the dynamic characteristics are varied greatly. This is the prime reason of difficulty of controlling the interleave PFC boost converter. In this paper, the robust digital controller using an A2DOF (Approximate 2-Degree-Of-Freedom) method for suppressing the variation of output voltage at a load sudden change with high power factor and low harmonic is proposed. Experimental studies using a micro-processor for controller demonstrate that this type of digital controller is effective to improve power factor and to suppress output voltage variation.

An adaptive slope compensation method for digital current mode control of dc-dc converters is proposed in this paper. The compensation slope is used for stabilizing the inner current loop in peak current mode control. In this method, the compensation slope is adapted with the variations in converter duty cycle. The adaptive slope compensation provides optimum controller operation in term of bandwidth over wide range of operating points. In this paper operation principle of the controller is discussed. The proposed controller is implemented in an FPGA to control a 100 W buck converter. The experimental results of measured loop-gain at different operating points are presented to validate the theoretical performance of the controller.

In this paper the energy performance comparison of active high-frequency power factor correctors for three control methods (borderline control, peak current control and average current control) is made. In MATLAB/Simulink environment models corresponding to each method of control were developed. Functional circuit diagrams, throttle current charts and load voltage charts of each corrector are given. Power factor correctors energy performance under the nominal load condition, under reduced and increased load resistance was researched.

A single-inductor dual-output (SIDO) buck converter with adaptive freewheel current and hybrid mode control is presented in this paper. It operates in pseudo-continuous conduction mode (PCCM) with single freewheel phase to reduce switching loss and minimize cross regulation. Freewheel current adjustment is implemented by detecting and control freewheel time, which can extend the load range and improve efficiency. For unbalanced load, this paper further proposed a hybrid PWM/hysteretic mode control scheme, which enables the two sub-converters to work at their own mode based on the load, independently of each other. The converter was designed with a 0.18μm CMOS process. Simulation results show that the efficiency reaches 87% in PWM mode. At light load, it is still higher than 80%.

Digital current mode control finds wide spread application in point of load power converters in DC nano-grid because of its technical benefits. However, finite current-loop sampling effects introduce undesirable sub-harmonic oscillations. This paper presents an analytical framework to investigate such nonlinear phenomena in a digitally current mode controlled boost converter. Discrete-time models for multi-sampled current loops and uniform sample with compensating ramp are derived under continuous conduction mode. We show that the discrete-time maps for such systems are discontinuous in nature. While the error voltage using a proportional-integral controller stays within the zero-error-bin (ZEB), the reference current becomes constant and 1-D maps of the inner current-loop can be used for stability analysis. Uniform sampling may lead to chaos, period doubling or stable period-1 behavior depending on slope of the compensating ramp. Multi-sampled current loop imposes several borders in the discrete parameter space and may eventually lead to high periodic behavior. In a counter-based compensating ramp, staircase effects may lead to sub-harmonic oscillation. Such instability eventually brings the error voltage outside the ZEB and 2-D map models have to be used for further investigating the nonlinear phenomena. A boost converter prototype was made. Digital current mode control is realized using an FPGA device. Test results demonstrate close agreement with the analysis.

Interactive digital control using PMBus protocol can significantly improve performance, efficiency and reliability in high frequency low voltage DC (LVDC) microgrid applications using online optimization through shared clock and data. Modeling and analysis of digitally controlled standalone DC-DC converters, considering finite sampling delays, have been well reported in the past; however, modeling and analysis of fast scale stability and performance limits, under finite sampling delay and clock shift, have not been investigated so far in digitally controlled LVDC microgrids. This paper considers an intermediate bus architecture (IBA), consisting of an intermediate bus converter (IBC) followed by a point-of-load (PoL) converter, under clock-synchronized digital current mode control (DCMC). Considering the IBA dynamics, a discrete-time (DT) framework is proposed, and DT small-signal models are derived for stability and performance analysis. It is shown that the clock shift between individual converters and the sampling delays of their corresponding digital controllers have significant impacts on the fast-scale stability of the overall IBA system, which may lead to severe fast-scale instability with complex nonlinear phenomena and resulting in much higher (inductor) current ripple and RMS quantities. Simulation case studies are presented, and the stability boundaries are found to be consistent with the analytical predictions. The proposed framework will be helpful to design stable digital control in DC microgrids.