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Power mad [low-power design

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Abstract

Designing for low power can drive you crazy. What is commonly referred to as low-power design actually comprises two different, but related activities. Power minimisation seeks to reduce average and instantaneous power consumption. This process will consider different modes of operation, such as standby or sleep mode, as well as dynamic and leakage power losses. Power integrity management on the other hand takes a look at the delivery of power to various parts of the chip. This process aims to minimise any negative power effects on design timing and functionality. To optimise power effects, a system should be properly architectured from word go and successively refined as the design proceeds. Design software can be used at all stages of chip design to detect and address critical issues. Indeed, the latest EDA tools can support high level register-transfer-level (RTL), optimise power, timing, and noise characteristics at the physical level, and also verify cell-based electrical characteristics for verification and sign-off.

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