PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability

In a single-flux-quantum (SFQ) circuit, almost all cells need to receive the clock signal which incurs a high clock routing overhead. Besides, the clock tree of an SFQ circuit requires the insertion of a clock splitter cell at every tree branching point which renders the conventional design flow of placement followed by clock tree synthesis ineffective to obtain a high quality clock tree with low clock skew. To address these issues, we propose a two-stage global placement methodology and a placement refinement algorithm after placement legalization. Our two-stage global placement methodology first applies a conventional global placement algorithm to place the cells in the given SFQ circuit evenly, which is followed by clock tree synthesis and clock splitter insertion, and then performs a second stage of global placement to re-place both the original cells and clock splitters at the same time. In the second global placement stage, the look-ahead legalization technique is used to spread out the original cells and the clock splitters, and the clock tree is re-synthesized several times to obtain an optimized clock tree topology such that there are little overlaps of the clock splitters with the original circuit cells. In addition, the total wirelength of data signals and clock signal is optimized concurrently. After legalizing the placement of all cells, our placement refinement method can be run to further reduce the clock skew. Compared with the previous state-of-the-art work, on average we can reduce the total half-perimeter wirelength and clock skew by 9% and 31%. respectively.

Legalization techniques are used both as a final stage and potentially as part of an iterative process of a global cell placement algorithm that distributes cells over a chip area in order to optimize criteria such as wirelength, routability, thermal dissipation etc. Although very efficient dynamic programming algorithms exist for standard cell placement legalization they usually incur high computational complexity, thus, might not be appropriate for acting as subcomponents in an iterative global placement process. On the other hand fast, single pass approaches such as Tetris heuristic, may offer low performance in terms of final placement quality. In this paper we turn our attention to legalization in standard cell placement under the presence of obstacles, with the aim of developing a fast yet efficient solution for the problem. The proposed heuristic is based on Tetris and involves judicious chip area splitting. Experiments with ibm circuits demonstrate that the resulting scheme, called OBstacle-aware Area Splitting Tetris (OBAST), offers significant performance improvement both in terms of solution quality and running time.

As the complexity and scale of FPGA circuits grows, resolving routing congestion becomes more important in FPGA placement. In this paper, we propose a routability-driven placement algorithm for large-scale heterogeneous FPGAs. Our proposed algorithm consists of (1) partitioning, (2) packing, (3) global placement with congestion estimation, (4) window-base legalization, and (5) routing resource-aware detailed placement. Experimental results show that our proposed approach can give routable placement results for all the benchmarks in the ISPD2016 contest and can achieve good result compared to the other wining teams of the ISPD2016 contest.

Due to the significant mismatch between global-routing congestions estimated during placement and the resulting design-rule violations in detailed routing, considering both global and detailed routability during placement is of particular importance for modern circuit designs. This paper presents an analytical standard-cell placement algorithm to optimize detailed routability with three major techniques: (1) A routability-driven wirelength model that directly minimizes routing congestion and wirelength simultaneously with no additional computational overhead in global placement. (2) A detailed-routability-aware whitespace allocation technique in legalization. (3) A multi-stage congestion-aware cell spreading method in detailed placement. Compared with the participating teams of the 2014 ISPD Detailed-Routing-Driven Placement Contest and a state-of-the-art routability-driven placer, our placer achieves the best quality in both detailed-routing violation and wirelength scores.

Highly-optimized placements may lead to irreparable routing congestion due to inadequate models of modern interconnect stacks and the impact of partial routing obstacles. Additional challenges in routability-driven placement include scalability to large netlists and limiting the complexity of software integration. Addressing these challenges, we develop lookahead routing to give the placer advance, firsthand knowledge of trouble spots, not distorted by crude congestion models. We also extend global placement to (i) spread cells apart in congested areas, and (ii) move cells together in less-congested areas to ensure short, routable interconnects and moderate runtime. While previous work adds isolated steps to global placement, our SIMultaneous PLace-and-Route tool SimPLR integrates a layer- and via-aware global router into a leading-edge, force-directed placer. The complexity of integration is mitigated by careful design of simple yet effective optimizations. On the ISPD 2011 Contest Benchmark Suite, with the official evaluation protocol, SimPLR outperforms every contestant on every benchmark.

We present a new approach to the placement problem. The proposed approach consists of analyzing the input circuit and deciding on a two-dimensional global grid for that particular input. After determination of the grid size, the placement is carried out in three steps: global placement, detailed placement and final optimization. We will show that the output of the global placement can also serve as a fast and accurate predictor. Current implementation is based on simulated annealing. We have put all algorithms together in a placement package called NRG (pronounced N-er-G). In addition to area minimization, NRG can perform timing-driven placement. Experimental results are strong. We improve TimberWolf's results (version 1.2, the commercial version which is suppose to be better than all university versions including version 7) by about 5%. Our predictor can estimate the wirelength within 10-20% accuracy offering 2-20x speedup compared with the actual placement algorithm.

As the complexity increases, power delivery network (PDN) optimization becomes a more important step in a modern design. In order to construct a robust PDN, most classic PDN optimization methods focus on adjusting the dimensions of power stripes. However, this approach becomes infeasible when voltage violation regions also have severe routing congestion. Hence, this paper proposes a delicate procedure to insert additional power stripes to reduce voltage violation while maintaining routability. In the beginning, IR-drop high related regions are identified to reveal those locations which are thirsty for more currents. Then, we solve a minimum-cost flow problem to find the topologies of power delivery paths (PDPs) from power sources to these regions and determine the widths of edges in each PDP so that enough currents can be provided to these regions. Moreover, vertical power stripes (VPSs for short) are inserted to the locations which have less routing congestion and severe voltage violations by the dynamic programming to reduce a probability to deteriorate routability. Finally, more wires will be inserted to IR-drop high related regions if there still exist voltage violations. Experimental results show that our method can use much less routing resource and induce less routing congestion to meet IR-drop constraint in industry designs.

With the advance of the communication technology and the massive flow of information across the internet, it is becoming urgent to keep the confidentiality of the transmitted information. Using the internet has been extended to several fields such as e-mail, e-commerce, e-learning, health and medicine, shopping, and so on. Cryptography is the study of different techniques for securing the communication between the sender and the receiver. One of the most known cryptosystems is Merkle–Hellman Knapsack Cryptosystem (MHKC). It is one of the earliest Public Key Cryptosystem (PKC) that is used to secure the messages between the sender and the receiver. Developing a powerful cryptosystem comes after studying the fragility points of the current cryptosystems. The Whale Optimization Algorithm (WOA) is one of the most recent nature-inspired meta-heuristic optimization algorithms, which simulates the social behavior of humpback whales. WOA has validated excellent performance in solving the continuous problems and the engineering optimization problems. This paper introduces a novel Modified version of WOA (MWOA) for cryptanalysis of MHKC. The sigmoid function is used to map the continuous values into discrete one. A penalty function is added to the evaluation function to deal with the infeasible solutions. The mutation operation is employed for improving the solutions. The results show that MWOA is more effective and robust than other algorithms in the literature.

Metaheuristic algorithms are optimization techniques inspired by natural processes, widely used to solve complex real-world problems. Traditional methods like swarm-based established optimizers often face challenges like premature convergence and high computational costs. The aim of this research is to develop a new optimization method for optimizing electric vehicle components and real-world problems. This research introduces a new chaotic fishing cat optimization algorithm (CFCO), a new optimization algorithm based on recent fishing cat optimization algorithm and chaotic maps. The chaotic maps are integrated into FCO to improve the balance between exploration and exploitation. This research is the first application of the CFCO to the optimum design of electric vehicle components in the literature. The algorithm is applied to various industrial design optimization problems, including structural optimization of cantilever beams, weight optimization of a coupling with a bolted rim, optimization of side profile of an electric vehicle battery enclosure, and heat exchanger economic optimization. The results demonstrate that the developed CFCO outperforms existing recent metaheuristic techniques, achieving superior efficiency and accuracy in industrial applications.

Runtime noise management systems can enforce power integrity without significantly increasing design margins. These systems typically respond to on-chip noise sensors to accurately capture voltage emergencies. Unfortunately, it remains an open problem in the literature how to optimally place a given number of noise sensors for best voltage emergency detection, or how to best set the threshold voltage for these sensors. In this paper, we formally define the problem of noise sensor placement along with a novel sensing quality metric to be maximized. We then put forward an efficient algorithm to solve it, which is proven to attain the best result in the class of polynomial complexity approximations. We further solve the problem to minimize the system failure rate subject to a given runtime performance loss (RPL) constraint. Experimental results on a set of industrial power grid designs show that, compared to a simple average-noise based heuristic and two state-of-the-art temperature sensor placement algorithms aimed at recovering the full map or capturing the hot spots at all times, the proposed method on average can reduce the miss rate of voltage emergency detections by 7.4x, 15x, and 6.2x, respectively. The trade-off between the system failure rate and the RPL is also presented. To the best of the authors' knowledge, this is the very first in-depth work on noise sensor deployment.

Crosstalk noise has become an important issue as technology scales down for timing and signal integrity closure. Existing works to fix crosstalk noise are mostly done at the routing or post routing stage, which may be too late. Since placement determines the overall routing congestion, which correlates with the coupling capacitance, which in turn correlates with the crosstalk noise, placement shall be a good level to do early noise mitigation. The only existing work for the crosstalk aware placement (to our best knowledge) is by Lou and Chen (2004), which uses the coupling capacitance map to guide placement. However, crosstalk is determined not only by the coupling capacitance, but also by many other factors, such as the driver resistance of the victim net and the coupling location (near source vs near sink coupling) (Cong et al., 2001). We introduce a concept of noise map which takes those factors into account. Guided by this accurate noise map explicitly, we propose an incremental placement technique to mitigate noise without disturbing the global placement order. Our incremental placement has two key steps, namely noise aware cell inflation and local refinement. Experimental results on industrial circuits show that our approach is able to reduce the number of top noise nets by 25% and improve the timing (300ps on the worst slack), with no wire length penalty or CPU overhead. Our incremental approach is also able to maintain the placement stability.

Ambient Intelligence (AmI) is an IT concept by which mobile users shall be seamlessly supported in their everyday activities. This includes interactions with remote resources as well as with their current physical environment. We have developed the so-called Ad hoc Service Grid (ASG) infrastructure that supports the latter form of interactions. It allows operators to cover arbitrary locations with ambient services in a drop-and-deploy fashion. An ambient service may autonomously distribute (replicate and migrate) within an ASG network to optimize its availability, response times, and network usage. In this article, we propose a fully decentralized, dynamic, and adaptive service placement algorithm for AmI environments like the ASG. This algorithm achieves a coordinated global placement pattern that minimizes the communication costs without any central controller. It does not even require additional communication among the replicas. Moreover, placement patterns stabilize if no changes occur in the environment while replicas still retain their ability to adapt. Mechanisms for self-organized placement of services are very important for AmI environments in general since they allow for autonomous adaptations to dynamic changes and, thus, remove the need for manual (re)configuration of a running system. We present a detailed evaluation of the algorithm's performance and compare it with three other algorithms to show its competitiveness. Furthermore, we discuss how the desired self-organizing behavior emerges from the interactions of a few simple, local rules that govern the individual placement decisions. In order to do so, we give an in-depth analysis of a series of emergent effects that are not directly encoded into the placement algorithm but stem from its collective dynamics.

A modern FPGA often contains an ASIC-like clocking architecture which is crucial to achieve better skew and performance. Existing conventional FPGA placement algorithms seldom consider clocking resources, and thus may lead to clock routing failures. To address the special FPGA clocking architecture, this paper presents a novel clock-aware placement algorithm for large-scale heterogeneous FPGAs. Our algorithm consists of three major stages: (1) a nonlinear global placement framework with clock fence region construction, (2) a clock-aware packing scheme, and (3) clock-aware legalization and detailed placement. We evaluate our results based on the 2017 ISPD Clock-Aware Placement Contest benchmark suite. Compared with the top three winners, the results show that our algorithm achieves the best overall routed wirelength. On average, our algorithm outperforms the top-3 winners by 3.6%, 7.5%, and 12.9% in routed wirelength, respectively.

Congestion mitigation and overflow avoidance are two of the major goals of the global routing stage. With a significant increase in the chip size and routing complexity,congestion and overflow have become critical issues in physical design automation. In this paper we present several routing algorithms for congestion reduction and overflow avoidance.Our methods are based on ripping up nets that go through the congested regions and replacing them with congestion-aware Steiner trees. We propose several efficient algorithms for finding congestion-aware Steiner trees and evaluate their performance using the ISPD routing benchmarks. We also show that the novel technique of network coding contributes to further improvements in routability and reduction of congestion. Accordingly, we propose an algorithm for identifying efficient congestion-aware network coding topologies and evaluate its performance.

Digital system designs are the product of valuable effort and know-how. Their embodiments, from software and hardware description language program down to device-level netlist and mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms to protect the rights of IP producers and owners. This paper establishes principles of watermarking-based IP protection, where a watermark is a mechanism for identification that is: (1) nearly invisible to human and machine inspection; (2) difficult to remove; and (3) permanently embedded as an integral part of the design. Watermarking addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch. We survey related work in cryptography and design methodology, then develop desiderata, metrics, and concrete protocols for constraint-based watermarking at various stages of the very large scale integration (VLSI) design process. In particular, we propose a new preprocessing approach that embeds watermarks as constraints into the input of a black-box design tool and a new postprocessing approach that embeds watermarks as constraints into the output of a black-box design tool. To demonstrate that our protocols can be transparently integrated into existing design flows, we use a testbed of commercial tools for VLSI physical design and embed watermarks into real-world industrial designs. We show that the implementation overhead is low-both in terms of central processing unit time and such standard physical design metrics as wirelength, layout area, number of vias, and routing congestion. We empirically show that the placement and routing applications considered in our methods achieve strong proofs of authorship and are resistant to tampering and do not adversely influence timing.