Provably good multicore cache performance for divide-and-conquer algorithms

Ideally, we could solve all memory performance problems by storing everything in high performance caches. However, the associated high-cost forces us to keep only a limited amount of working sets of data in these caches and the replacement of disposable blocks of data with the desired one is a fundamental property to caches. Ultimately, the performance of a cache is heavily influenced by the replacement policy it uses. In this paper, we conduct a comparative analysis of a few replacement policies currently in use from traditional strategies to the ones that attempt to emulate optimal replacement and simulate a few replacement strategies to test the performance of multilevel cache by configuring the cache memory subsystem in the Multi2sim simulator. We have focused on the shared nature of the last Level Cache (LLC) which includes many coherence problems. This is where directories and coherence protocols come into play. However, the blocks suffer when the directory entries are themselves evicted from the directory. In this paper, we look into a cache coherence mechanism that instead of evicting the block from the private caches when the directory entry is evicted, rather than storing the entry in the LLC slice. This guarantees freedom from the Directory Eviction Victim Blocks (DEVB). We analyze the performance of our proposed replacement technique, namely, coalesce private or spill shared (CPOSS) by varying the size and associativity of the sparse directory by providing the workload from Parsec, Splash2 and FFTW benchmarks and we observe that the CPOSS outperforms the existing least recently used (LRU) in slice LLC banks in Multicore processors.

Large-scale MIN-based shared-memory multiprocessor systems have long shared memory latency. Private caches can improve memory access latency but they may suf fer from the cache coherence problem and potentially lower data locality due to data sharing and multiproces sor scheduling. These two problems also increase shared memory load and may result in frequent memory stalls. In this paper, we evaluate the performance of memory caches, a cache memory placed in front of shared memory, in a large-scale multiprocessor system in the presence of pro cessor caches. The memory cache is shown to have good performance and scalability.

The performance of modern multicore processes largely depends on the performance of their shared Last Level Cache (LLC). A larger LLC can reduce misses while increasing access latency. Tile-based chipmultiprocessors (TCMP) are also proposed with two levels of shared caches to handle such situations. Among the two levels of shared caches, the bottom level is designed with DRAM technology for better capacity, and the upper level is designed with SRAM technology for better latency. Because it is in the last level, the LLC is the DRAM-based shared cache. Both the shared caches are normally divided into multiple banks. The core in such TCMPs can have its own private cache above these two levels of shared caches. Process variation has been observed to have a much greater impact on DRAM-based memory chips than on SRAM-based memories. Hence, the banks of the DRAM-based LLC may not behave uniformly. Some of the banks may experience high energy costs and access latency because of PV. In this work, we have proposed a replacement policy for the SRAM-based shared cache (upper-level shared cache), which reduces the requirements to access the PV-affected LLC banks significantly. This is achieved by relaxing the blocks of the affected LLC banks to remain in the upper-level shared cache (SRAM-based) for a longer time. The experimental analysis found that the proposed replacement policy improves performance by 13%, 10%, and 6% as compared to three existing replacement policies.

: Future CMPs will have more cores and greater onchip cache capacity. The on-chip cache can either be divided into separate private L2 caches for each core, or treated as a large shared L2 cache. Private caches provide low hit latency but low capacity, while shared caches have higher hit latencies but greater capacity. Victim replication was previously introduced as a way of reducing the average hit latency of a shared cache by allowing a processor to make a replica of a primary cache victim in its local slice of the global L2 cache. Although victim replication performs well on multithreaded and single-threaded codes, it performs worse than the private scheme for multiprogrammed workloads where there is little sharing between the different programs running at the same time. In this paper, we propose victim migration, which improves on victim replication by adding an additional set of migration tags on each node which are used to implement an exclusive cache policy for replicas. When a replica has been created on a remote node, it is not also cached on the home node, but only recorded in the migration tags. This frees up space on the home node to store shared global lines or replicas for the local processor. We show that victim migration performs better than private, shared, and victim replication schemes across a range of single threaded, multithreaded, and multiprogrammed workloads, while using less area than a private cache design. Victim migration provides a reduction in average memory access latency of up to 10% over victim replication.

Multicore Processors and Systems provides a comprehensive overview of emerging multicore processors and systems. It covers technology trends affecting multicores, multicore architecture innovations, multicore software innovations, and case studies of state-of-the-art commercial multicore systems. A cross-cutting theme of the book is the challenges associated with scaling up multicore systems to hundreds of cores. The book provides an overview of significant developments in the architectures for multicore processors and systems. It includes chapters on fundamental requirements for multicore systems, including processing, memory systems, and interconnect. It also includes several case studies on commercial multicore systems that have recently been developed and deployed across multiple application domains. The architecture chapters focus on innovative multicore execution models as well as infrastructure for multicores, including memory systems and on-chip interconnections. The case studies examine multicore implementations across different application domains, including general purpose, server, media/broadband, network processing, and signal processing. Multicore Processors and Systems is the first book that focuses solely on multicore processors and systems, and in particular on the unique technology implications, architectures, and implementations. The book has contributing authors that are from both the academic and industrial communities.

Given the ubiquity of cache-based machines, it is important to analyze how well a program or an algorithm uses the cache. There is no widely accepted measure of cache complexity, yet the cache complexity is often more important to performance than the measures of time and space complexity. This paper presents Data Movement Distance (DMD) to measure the cost of cache complexity for algorithms, demonstrates its use, and discusses it as a measure of locality. Since processor speeds are getting ever faster, one of the main bottlenecks in modern computing is moving the needed data into and around the processor. DMD measures the efficiency of the algorithm in this sense and therefore may be a much-needed complement to the conventional analysis of computation complexity. In this paper, we give an overview of DMD and some basic results. These will be expanded upon in future work.

The number of chip pins is limited due to the cost and reliability issues of sophisticated packages, and it is predicted that the chip pin count will be overstretched to satisfy the requirements of both power delivery and memory access. The gap between the achievable pin count and the demand will increase as the technology scales, due to the increasing computation resources and supply current. Pin reduction techniques are thus required for continued computing performance growth. In this article, we propose a chip pin constraint alleviation strategy, through on/off-chip power delivery system co-design, to effectively reduce the demand for power pins. An analytical model of a power delivery system, consisting of on/off-chip regulators and a power delivery network, is proposed to evaluate the influence of regulator design and package conduction loss. By combining this model with a multi-core processor model of performance and memory bandwidth requirements, we characterize the entire multi-core processor system to investigate the relationship between the chip pin constraint and performance in multi-core processor scaling and the effectiveness of our strategy. Experiments show that with the conventional power delivery system design, the chip pin constraint severely limits the performance growth as the technology scales. Using the on/off-chip power delivery system co-design, our strategy achieves a significant pin count reduction, for example, 31.3% at the 8nm technology node, compared to the conventional design with the same chip performance, while, provided with the same chip pin count, it is able to improve, by 35.0%, the chip performance at 8nm compared to the conventional design. For real applications of different parallelism, our strategy outperforms its counterpart, with a 23.7% performance improvement on average at the 8nm technology node.

With the advent of multi-core processors, parallel execution of multiple tasks has become a common practice. Various scheduling algorithms have addressed this issue considering multiprocessor systems. Most of these algorithms target application level parallelism. Task level parallelism within an application can be exploited using shared memory architecture such as multi-core processor or in a distributed computing environment. In this paper, we propose a static scheduling algorithm that generates a schedule that can be optimized for one or all parameters including execution time, number of processors, and efficiency of processors. The input to this scheduler is a task dependency matrix is generated using dependency analysis technique. Efficiency of this scheduler is high because it uses multiple parameters such as task wait time, number of tasks whose dependency gets resolved by scheduling a task, and task execution time. The paper concludes with an example of applying this technique to a set of tasks.

The task allocation problem with constant communication

We consider the problem of scheduling tasks on multiprocessor architectures in the presence of communication delays. Given a set of dependent tasks, the scheduling problem is to allocate the tasks to processors such that the pre-specified precedence constraints among the tasks are obeyed and certain cost-measures (such as the computation time) are minimized. Several cases of the scheduling problem have

In the field of parallel computing, load balancing of parallel simulations is considered as a fundamental problem. The primary goal is to evenly distribute computing load across multiple processors while minimizing processor-to-processor communication. A prevalent approach to solving the problem of balancing is based on a graph model. To balance the load between k processors, we partition the graph into k parts, each one is assigned to a processor. This problem is difficult to solve, but effective heuristics have been proposed, including those based on a multilevel approach, used by most graph partitioning tools. All partitioning methods are only relevant if the number of processors is fixed. It is essential to choose the right number of processors for a simulation to get good performance and more efficiency.In this paper, we test several graphs partitioning using the metis framework then we try to find the optimal number of processors, named in this paper p* to execute a simulation and the max speed up that we can reach using parallelization. We also investigate the intrinsic graph characteristics that affect these parameters.

Data or instructions that are regularly used are saved in cache so that it is very easy to retrieve for the purpose of increase the cache performance. Evaluating the execution of multi-core systems the part of the cache memory is very important. A multicore processor is shared circuit in which two or more processors are joined to enhance the performance and perform multiple tasks. This paper describes the performance of cache memory based on cache access time, miss rate and miss penalty. Cache mapping methods are defined to increase the performance of cache but it face many difficulties. Some methods and algorithms are used to decrease these difficulties. In this paper describes the study of recent competing processors to evaluate the cache memory performance.

The number of processors is increasing, but the usefulness of parallel computation is not better leveraged due to the inflexibility of design and implementation for multiprocessor embedded system applications. A higher level abstraction (i.e., a parallel programming framework) can ease the programmers to define parallelism for tasks in an application but designers still face the complexity of mapping high-level requirements to the syntax and semantics of a parallel programming interface. Nevertheless, embedded system applications execute various periodic tasks that are carried out repeatedly within a certain time interval and these tasks may be able to run in parallel to utilize the system efficiently. Therefore, in this paper, we propose a parallel loop-based task construct approach to automate the design process of embedded system applications from AADL models for a parallel programming framework. To illustrate the applicability of our mechanism, we use a well-known parallel programming interface called OpenMP to demonstrate the automation process in mapping tasks over multiple processor cores. To ensure meeting high-level requirements of embedded system applications, we analyze the existing OpenMP scheduling mechanisms and propose a layer of adaptation. We show that our proposed adaptation layer facilitates a tighter execution time bound for time-sensitive tasks or a better throughput for tasks that require higher quality of service. Thus, the proposed design automation framework is applicable for a variety of applications with different quality of service (QoS) requirements preserved at the lower level.

Multiple CPU and GPU cores are integrated together in a typical CE system with shared caches. As the CPU and GPU applications have different characteristics in cache accesses there can be performance penalty. This paper presents a bypass-based shared cache management method to improve such penalty in CE systems. This method dynamically analyzes the cache sensitive features of CPU and GPU application during the execution. It considers the current access characteristics of applications when dealing with the GPU access request, real time to determine whether the GPU application is accessing the memory or accessing the shared cache, through the dynamic adjustment to make it better to adapt to different applications.

Finite state automata are of fundamental importance in theory as well as applications in computer science. This dissertation presents several parallel algorithms for processing of them, including minimizing the number of states for a given finite state automaton, finding homing sequences for a given finite state automaton, converting a regular expression into an $\\varepsilon$-free nondeterministic finite automaton. Implementation of some algorithms, as well as their experimental results, are also given. For minimization of deterministic finite automata, we present a parallel algorithm and discuss its implementation on a practical parallel machine using data parallel and message passing paradigms. Its time complexity on a p processor EREW PRAM $(p\\le n)$ for inputs of size n is $O({n\\log\\sp2n\\over p}+\\log n\\ \\log p)$ uniformly on almost all instances. The work done by our algorithm is thus within a factor of $O(\\log n)$ of the best known sequential algorithm. The space used by our algorithm is linear in the input size. The actual resource requirements of our implementations are consistent with these estimates. For finding homing sequences of deterministic finite automata, we present both deterministic and randomized algorithms. Two randomized algorithms of time complexity $O(log\\sp2n)$ are given. One of the randomized algorithms produces a homing sequence of length $O(n\\ log\\sp2n)$ for almost all DFA's with n states. The deterministic algorithm is based on a well known sequential algorithm. The implementation of the deterministic parallel algorithm shows that it can handle randomly generated instances with millions of states, and all DFA's with thousands of states using currently available parallel machines. Finally, we present an efficient parallel algorithm for converting a regular expression into an $\\varepsilon$-free nondeterministic finite automaton. The resulting automaton is natural representation of a regular expression and has some important and practical uses in the document processing area. The time complexity of the algorithm is $O(\\log n)$ and the number of processors used is $O(n\\sp2).$