Rank-metric Encryption on Arm-Cortex M0

Error-Correcting Code (ECC) provides robust readability to both linear and two-dimensional (2D) barcodes, particularly for localized damage. Many ECC approaches, however, are based on assumptions about the types of damage or the communication channel used. As the applications for barcodes rapidly evolve with the increasing ubiquity of mobile cameras, an evaluation of the trade off between ECC and simply increasing the size of the bar code modules is required. This article compares the impact of simply changing the module size versus using error correction–which exhausts a percentage of the symbol area without adding payload data. For three typical nondestructive types of damage–the print-scan cycle, low quality printing, and blurring–investigated here, there is compelling support for increasing the size of the barcode modules and foregoing ECC. Freeing barcodes from the need for ECC provides an additional advantage: namely, the barcodes can be scrambled to be unreadable under the defined barcode specification without a change in size or appearance. This is in contrast to the use of ECC, for which only a small minority of rearrangements of the data in the barcode would be "decodable." Thus, without the use of ECC, it is much harder for a would-be counterfeiter or other dishonest party to determine the scrambling approach. Additionally, we can create 2D barcodes that are not "readable" using commercially available reading software, except where so desired. These results are discussed in light of destructive damage and for different applications of 2D bar codes.

The continuous raise in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, computer memory is affected by Single Cell Upsets (SCU) and Multiple Cell Upsets (MCU). A common method to tolerate errors in this element is the use of Error Correction Codes (ECC). The addition of an ECC introduces a series of overheads: silicon area, power consumption and delay overheads of encoding and decoding circuits, as well as several extra bits added to allow detecting and/or correcting errors. ECC can be designed with different parameters in mind: low redundancy, low delay, error coverage, etc. The idea of this paper is to study the effects produced when adding an ECC to a microprocessor with respect to overheads. Usually, ECC with different characteristics are continuously proposed. However, a great quantity of these proposals only present the ECC, not showing its behavior when using them in a microprocessor. In this work, we present the design of an ECC whose main characteristic is a low number of code bits (low redundancy). Then, we study the overhead this ECC introduces. Firstly, we show a study of silicon area, delay and power consumption of encoder and decoder circuits, and secondly, how the addition of this ECC affects to a RISC microprocessor.

Technology advances have recently enabled the use of DRAMs into logic integrated circuits. These embedded DRAMs can be used to efficiently implement caches since DRAMs require substantially less area than SRAMs. One challenge for DRAM based caches is that a small time between refreshes is needed to ensure data retention. These refreshes increase the power consumption even when the cache is idle. To mitigate this issue, the use of longer times between refreshes combined with the use of Error Correction Codes (ECCs) has been recently proposed. The idea is that the time between refreshes can be increased significantly while only causing data retention failures on a small percentage of the cells. Then those errors can be corrected by the ECC. For this scheme to be efficient the number of additional bits required by the ECC should be small. This is achieved by using large data blocks for the ECC which in turns means that a large data block has to be accessed even when only a small portion of it is needed. This has no effect on idle power consumption but increases the dynamic power consumption and reduces the effective memory bandwidth. In this paper, a technique to mitigate this issue is proposed. It enables better granularity in the read data accesses by partitioning the ECC block into two sub-blocks and modifying the error detection and correction processes. This reduces the dynamic power consumption and increases the available memory bandwidth while requiring only a moderate increase in the number of additional bits.

This article explores the emerging trends in cybersecurity in response to the advent of quantum computing, focusing on the development of quantum-safe encryption methods. It begins by examining the vulnerabilities of traditional encryption algorithms like RSA and ECC to quantum attacks, particularly through Shor's algorithm. The article then delves into post-quantum cryptography (PQC), discussing key approaches such as lattice-based cryptography, hash-based signatures, and code-based cryptography, along with their advantages and challenges. Quantum Key Distribution (QKD) is explored as an alternative method for secure communication, leveraging quantum mechanics principles. The article also covers the ongoing standardization efforts led by organizations like NIST, highlighting the progress made in establishing quantum-resistant algorithms and the challenges in their widespread adoption. Finally, it addresses the future-proofing of encryption systems, discussing the balance between quantum resistance and current security needs, the maintenance of confidentiality, integrity, and authentication, and potential hybrid approaches. Throughout, the article emphasizes the critical nature of these developments in ensuring long-term data security in a world where quantum computers may soon become a reality.

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Resiliency will be one of the toughest challenges in future exascale systems. Memory errors contribute more than 40% of the total hardware-related failures and are projected to increase in future exascale systems. The use of error correction codes (ECC) and checkpointing are two effective approaches to fault tolerance. While there are numerous studies on ECC or checkpointing in isolation, this is the first paper to investigate the combined effect of both on overall system performance and power. Specifically, we study the impact of various ECC schemes (SECDED, BCH, and chip-kill) in conjunction with checkpointing on future exascale systems. Our simulation results show that while chipkill is 13% better for computation-intensive applications, BCH has a 28% advantage in system energy-delay product (EDP) for memory-intensive applications. We also propose to use BCH in tagged memory systems with commodity DRAMs where chipkill is impractical. Our proposed architecture achieves 2.3× better system EDP than state-of-the-art tagged memory systems.

In Ultra Deep Sub Micron (UDSM) Technology, accomplishment of error free data transmission through Network on Chip (NoC) interconnect becomes impractical. This difficult state is widely managed by the use of Error Correction Codes (ECC) in NoC. A novel Hamming based Multiple Transient Error Correction (HMTEC) code is proposed to enhance the NoC interconnect reliability. Implementation of this code corrects all single bit errors and most of the combinations of errors upto 8 bits for a flit size of 32. Furthermore, this code allows error correction in both data and redundant bits. This coding method is performed at lower power consumption, area occupancy and delay when measured against similar codes proposed in recent years.

In this work, we present a systematic study of Side-Channel Attacks (SCA) and Fault Injection Attacks (FIA) on structured lattice-based schemes, with main focus on Kyber Key Encapsulation Mechanism (KEM) and Dilithium signature scheme, which are leading candidates in the NIST standardization process for Post-Quantum Cryptography (PQC). Through our study, we attempt to understand the underlying similarities and differences between the existing attacks while classifying them into different categories. Given the wide variety of reported attacks, simultaneous protection against all the attacks requires to implement customized protections/countermeasures for both Kyber and Dilithium. We therefore present a range of customized countermeasures, capable of providing defenses/mitigations against existing SCA/FIA, and incorporate several SCA and FIA countermeasures within a single design of Kyber and Dilithium. Among the several countermeasures discussed in this work, we present novel countermeasures that offer simultaneous protection against several SCA- and FIA-based chosen-ciphertext attacks for Kyber KEM. We implement the presented countermeasures within two well-known public software libraries for PQC: (1) pqm4 library for the ARM Cortex-M4-based microcontroller and (2) liboqs library for the Raspberry Pi 3 Model B Plus based on the ARM Cortex-A53 processor. Our performance evaluation reveals that the presented custom countermeasures incur reasonable performance overheads on both the evaluated embedded platforms. We therefore believe our work argues for usage of custom countermeasures within real-world implementations of lattice-based schemes, either in a standalone manner or as reinforcements to generic countermeasures such as masking.

The impending realization of scalable quantum computers will have a significant impact on today's security infrastructure. With the advent of powerful quantum computers public key cryptographic schemes will become vulnerable to Shor's quantum algorithm, undermining the security current communications systems. Post-quantum (or quantum-resistant) cryptography is an active research area, endeavoring to develop novel and quantum resistant public key cryptography. Amongst the various classes of quantum-resistant cryptography schemes, lattice-based cryptography is emerging as one of the most viable options. Its efficient implementation on software and on commodity hardware has already been shown to compete and even excel the performance of current classical security public-key schemes. This work discusses the next step in terms of their practical deployment, i.e., addressing the physical security of lattice-based cryptographic implementations. We survey the state-of-the-art in terms of side channel attacks (SCA), both invasive and passive attacks, and proposed countermeasures. Although the weaknesses exposed have led to countermeasures for these schemes, the cost, practicality and effectiveness of these on multiple implementation platforms, however, remains under-studied.

Objectives. Programmable logic integrated circuits of the field programmable gate array (FPGA) type based on static configuration memory are widely used in the electronics of onboard spacecraft systems. Under the influence of space radiation, errors may occur in the FPGA configuration memory. The main methods of protection against such errors involve various options for reservation triggers, as well as the use of error-correcting codes in special error detection and correction circuits. The purpose of the present work is to determine which error-correcting codes are best suited to the implementation of internal scrubbing of the FPGA configuration memory taking redundancy into account.Methods. The paper analyses various methods for scrubbing FPGA configuration memory, which are used to correct errors caused by the action of space radiation. It is proposed to increase the efficiency of internal scrubbing of the FPGA configuration memory using codes that correct both single- and double-adjacent SEC-DED-DAEC errors. In this case, the need to perform external scrubbing of the configuration memory is reduced by overwriting it with a reference configuration from non-volatile radiation-resistant memory; in this way, FPGA downtime caused by the external scrubbing procedure is reduced. Due to the known SEC-DED-DAEC codes having a non-zero probability of erroneous detection and subsequent erroneous correction of a double non-adjacent error, as well as various redundancy and implementation complexities, a study was made of the most efficient code for internal scrubbing.Results. The results showed that the Datta, Neale and Hoyoon–Yongsurk codes are optimal from the indicated positions. Recommendations are given for selecting a specific code depending on the specific requirements for a particular planned space mission.Conclusions. The study confirms the effectiveness of protecting the memory of programmable logic by using two-error-correcting codes.

The ongoing transition to post-quantum cryptography has highlighted the need for digital signature schemes offering diverse performance and security trade-offs. Among the candidates in NIST’s ongoing post-quantum signature standardisation process is FAEST, a scheme built upon the Vector Oblivious Linear Evaluation in-the-Head (VOLEitH) paradigm introduced in 2023. VOLEitH enables efficient zero-knowledge proofs with competitive signature sizes under conservative assumptions, allowing FAEST to rely primarily on the one-wayness of the Advanced Encryption Standard (AES). Despite their promising efficiency, VOLEitH-based signature schemes have remained relatively unexplored from a physical security perspective. In this paper, we present the first side-channel security evaluation. Specifically, we demonstrate two single-trace, deep learning-assisted power analysis attacks on the masked implementation of FAEST by Aranha, Degn, Eilath, Nielsen, and Scholl. These attacks exploit leakage from witness bits and VOLE tag computations, recovering the full secret key with success probability above 0.99 from a single signature on an ARM Cortex-M4 processor. We further analyse how the VOLEitH construction enables profiling of VOLE tags without knowledge of the secret key and how even partial leakage of these tags compromises security. Finally, we discuss practical countermeasures to mitigate such leakages and strengthen the physical resilience of VOLEitH-based signature implementations.

Beginning with the proposal of the McEliece cryptosystem in 1978, code-based cryptography has positioned itself as one of main categories in post-quantum cryptography (PQC). To date, the algebraic security of certain variants of McEliece cryptosystems has been challenged many times, although some of the variants have remained secure. However, recent studies on code-based cryptography have focused on the side-channel resistance since previous studies have indicated that the existing algorithms were vulnerable to side-channel analysis. In this paper, we propose the first side-channel attack on the Hybrid McEliece Scheme (HyMES) using only a single power consumption trace. HyMES is a variant of the McEliece system that provides smaller keys, along with faster encryption and decryption speed. By exploiting joint distributions of nonlinear functions in the decryption process, we were able to recover the private key of HyMES. To the best of our knowledge, this is the first work proposing a side-channel analysis based on a joint distribution of the leakages on the public-key system.

Chapter 1 - Introduction

Lattice-based cryptography has emerged as a powerful paradigm for constructing secure cryptographic primitives, offering resistance to quantum attacks and providing a versatile framework for building post-quantum cryptographic systems. This research paper provides an in-depth exploration of lattice-based cryptography, focusing specifically on its applications for problems based on Ring Learning with Errors (RLWE). We analyze the fundamental concepts of lattice theory, delve into the RLWE problem, and highlight the security properties and challenges associated with lattice-based schemes. Furthermore, we discuss various real-world applications of lattice-based cryptography, demonstrating its potential for secure communication, privacy-preserving protocols, and post-quantum cryptography.

Side-channel attacks are a prominent threat to the security of cryptographic implementations. Differently from the traditional black-box attacks, which exploit the inputs and outputs of cryptographic schemes, side-channel attacks partially access the inner working of the scheme as well, by observing the physical leakage emitted by the device executing cryptographic algorithms. A notable example is the class of power-analysis attacks, which exploits the power consumption of the underlying device to recover the secret keys of the implemented cryptosystem. Since their first presentation in the late 1990s, the problem of securing cryptographic systems in the presence of side-channel leakages received significant attention by the cryptographic community. In particular, the theory community has concentrated its research efforts on formally modeling the side-channel leakages and on designing cryptographic schemes \textit{provably} secure in such leakage models. However, conceiving a formal model that realistically captures possible physical leakages and constructing primitives sufficiently efficient to be deployed in practice are still challenging research objectives. This research area is usually referred to as leakage-resilient cryptography. In this dissertation, we examine three main research directions. The first one focuses on the technique of masking, which is the most popular approach to counteract power-analysis attacks. In this context, our work analyzes possible methods to improve the efficiency of masked implementations, with the goal of overcoming the decrease in performance, which is a common drawback of masking. In particular, we provide new and more efficient algorithms for the computation of basic operations in two kinds of masking schemes: the Boolean masking and the Inner Product masking. The second research direction of this work addresses the problem of formalizing security requirements for hardware implementations. While provable security of software-oriented masking has been studied since the origin of leakage resilient cryptography, the more complex task of formally proving the security of hardware-oriented masking is receiving attention by the community only recently. We discuss the different challenges of this field, and we introduce a new theoretical model, the robust probing model, capturing the conditions required for securely implementing complex algorithms in practice, providing a guide to practical implementers. Finally, the last part of this work is concerned with the protection of algorithms employed in lattice-based constructions, which are studied in the field of post-quantum cryptography. While several works investigate the application of masking schemes to standard cryptosystems, for most post-quantum schemes this is still an ongoing research. We contribute to this research area, by applying the masking countermeasure to a binomial sampler which is at the base of many lattice-based cryptosystems.