Design, Implementation and Evaluation of a Low Redundant Error Correction Code

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Multiple cell upsets (MCUs) become more and more problematic as the size of technology reaches or goes below 65 nm. The percentage of MCUs is reported significantly larger than that of single cell upsets (SCUs) in 20 nm technology. In SRAM and DRAM, MCUs are tackled by incorporating single-error correcting double-error detecting (SEC-DED) code and interleaved data columns. However, in content-addressable memory (CAM), column interleaving is not practically possible. A novel error correction code (ECC) scheme is proposed in this paper that will cater for ever-increasing MCUs. This work demonstrated that m parity bits are sufficient to cater for up to m-bit MCUs, with an understanding of the physical grouping of MCUs. The results showed that the proposed scheme requires 85% fewer parity bits compared to traditional Hamming distance based schemes.

Multiple Cell Upsets (MCUs) induced by ionizing radiation in memories are becoming more likely to happen due to the continuous technology scaling down. Error Correction Codes (ECCs) are applied for recovering the stored information into its original state providing reliable computer systems. Several ECC are able to deal with MCUs, however, the higher the robustness of an ECC, more area, and energy is required for its implementation, becoming a problem if applied in application where resources are scarce. This article presents the implementation and evaluation of the Matrix Region Section Code (MRSC), a new algorithm for the detection and correction of multiple transient faults in volatile memories with low cost implementation. The experimental results measuring error coverage composed by detection and correction analysis, area, power and delay overheads have shown that MRSC is an excellent option to counteract with MCUs.

Due to vast integration density in CMOS technology, faults in the embedded or external memory have been increased. This manifests as single-cell upsets (SCU) and multiple cell upsets (MCU) for function, especially in flash memories. Flash memory provides far greater storage capacity at lower operating cost than SDRAM. Memories that operate in harsh environment like space can suffer from multiple errors. Due to the faults, data can be flipped from 1 to 0 or 0 to 1 or sometimes the message bits even get deleted. So, an embedded error correction code-based functional block is used along with dense memory, to ensure that the errors do not cause data corruption. This paper presents a method to protect memories from multiple cell upsets by adding redundancy. The error detection and correction can be done by using flexible unequal error control code (FUEC)-based design. The FUEC can detect and correct double, triple, and quadruple adjacent error. By using this method, low redundancy can be achieved in memory. The ECC engine was designed successfully, verified, and ready for integration to the memory. The design details are discussed below.

Error-Correcting Code (ECC) provides robust readability to both linear and two-dimensional (2D) barcodes, particularly for localized damage. Many ECC approaches, however, are based on assumptions about the types of damage or the communication channel used. As the applications for barcodes rapidly evolve with the increasing ubiquity of mobile cameras, an evaluation of the trade off between ECC and simply increasing the size of the bar code modules is required. This article compares the impact of simply changing the module size versus using error correction–which exhausts a percentage of the symbol area without adding payload data. For three typical nondestructive types of damage–the print-scan cycle, low quality printing, and blurring–investigated here, there is compelling support for increasing the size of the barcode modules and foregoing ECC. Freeing barcodes from the need for ECC provides an additional advantage: namely, the barcodes can be scrambled to be unreadable under the defined barcode specification without a change in size or appearance. This is in contrast to the use of ECC, for which only a small minority of rearrangements of the data in the barcode would be "decodable." Thus, without the use of ECC, it is much harder for a would-be counterfeiter or other dishonest party to determine the scrambling approach. Additionally, we can create 2D barcodes that are not "readable" using commercially available reading software, except where so desired. These results are discussed in light of destructive damage and for different applications of 2D bar codes.

Error correction codes are used in semiconductor memories to protect information against errors. Simple error correction codes are preferred due to their low redundancy and encoding/decoding latency. Hamming codes are simple and can be easily built for any word length. They only allow single error correction, so a multiple error can lead to a wrong decoding. Multiple errors often manifest as burst errors, and they are becoming more frequent as integration scale increases. This paper proposes modified Hamming codes, with the same redundancy and coverage as the original versions, but adding short burst error detection. Three code examples, with different error correction and detection capabilities, are presented. They are especially well-suited for memories, where the length of the data word is commonly a power of 2, and low redundancy and fast and simple encoder and decoder circuits are required.

Technology advances have recently enabled the use of DRAMs into logic integrated circuits. These embedded DRAMs can be used to efficiently implement caches since DRAMs require substantially less area than SRAMs. One challenge for DRAM based caches is that a small time between refreshes is needed to ensure data retention. These refreshes increase the power consumption even when the cache is idle. To mitigate this issue, the use of longer times between refreshes combined with the use of Error Correction Codes (ECCs) has been recently proposed. The idea is that the time between refreshes can be increased significantly while only causing data retention failures on a small percentage of the cells. Then those errors can be corrected by the ECC. For this scheme to be efficient the number of additional bits required by the ECC should be small. This is achieved by using large data blocks for the ECC which in turns means that a large data block has to be accessed even when only a small portion of it is needed. This has no effect on idle power consumption but increases the dynamic power consumption and reduces the effective memory bandwidth. In this paper, a technique to mitigate this issue is proposed. It enables better granularity in the read data accesses by partitioning the ECC block into two sub-blocks and modifying the error detection and correction processes. This reduces the dynamic power consumption and increases the available memory bandwidth while requiring only a moderate increase in the number of additional bits.

Soft errors have been a concern in memories for many years. In older technologies, soft errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets (MCUs) that affect a group of nearby cells have become more common. This trend is expected to continue making MCUs more frequent and also increasing the number of cells affected. To avoid data corruption in memories, Error Correction Codes (ECCs) are used. Single Error Correction (SEC) codes that can correct one bit error per word are effective only against single errors. To protect against MCUs, one option is to use more sophisticated error correction codes like for example, Orthogonal Latin Squares Codes (OLSC). In this paper, a modification of the OLSC decoding algorithm is proposed for codes that can correct two random errors. This modification has little impact on circuit complexity and enables triple adjacent error correction which is interesting when MCUs are present.

为了提高纠错编码（ECC）的有效性，先进的静态随机存储器（SRAM）多采用位交错结构。但是，在没有物理版图信息的情况下，位交错设计使得从辐照测试数据中提取出多单元翻转（MCU）变得更加困难。运用Bi离子辐照带有ECC的65 nm SRAM器件，研究了该款器件在重离子辐照下的敏感性。为伪多位翻转（FMBU）以及MCU的数据分析提供了理论指导和帮助，完善了判别MCU的基本法则。除此之外，研究结果表明，ECC的汉明编码对于纳米器件的效果不够理想。在未来的空间应用中，需考虑更高层次的编码算法来抵抗单粒子翻转。 In order to improve the robustness of error-correcting codes (ECC), modern static random access memory (SRAM) always use bit-interleaving structure. However, in the absence of physical layout information, the bit-interleaving design makes it more difficult to extract the multiple-cell upset (MCU) from the test data. In this paper, the sensitivity of Bi ion irradiation was investigated in a 65 nm technology SRAM with ECC. The experimental results provide a theoretical guidance and help for the fake multiple-bit upset (FMBU) and MCU data analyzing, which improve and perfect the basic rules extracting MCU from the test data. In addition, the results show that the performance of hamming encoding is not ideal in Nano scale SRAM. In the future of space applications, it is necessary to consider more advanced algorithms to against SEU.

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

Error-correcting codes (ECC) are widely used during data transfer in wireless communication systems as well as in computer memory architectures. The error-correcting process is based on sending data with extra parity bits and decoding the received data for error correction. The first error detection and correction code, introduced in 1950, Hamming Code (7,4) is a linear error-correcting code able to detect and correct a single-bit error by encoding 7-bit data from 4-bit data, including 3 parity bits. Previous efforts using unipolar resistive random access memory (ReRAM) based in-memory computation of Hamming Code (7,4) resulted in 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> times lower power consumption compared to GPU and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> times less than CPU-based computations. However further reduction of power consumption can be achieved by vector-matrix multiplication (VMM) using bipolar ReRAM arrays. In the VMM based approach, an encoding or decoding code matrix is stored in the array where it leverages the nonvolatile properties of ReRAM. With the VMM approach, the total number of computation cycles is not limited by the endurance of the ReRAM devices. Here we report the first experimental results of encoding and decoding Hamming code (7,4) using 1 transistor 1 hafnium oxide-based ReRAM (1T1R) arrays fabricated using 65nm CMOS technology. Our results show bipolar 1T1R arrays can correctly encode 4-bit message data to 7 bit encoded data as well as error position detection with overall 3 fold less power consumption than previously reported unipolar ReRAM crossbar array-based computation. Furthermore, we propose and simulate a peripheral circuit to convert the analog column output from a 1T1R array to single-bit binary output using the Cadence Spectre simulator. Our results pave the way for using a memristor-based fast and scalable hardware solution for encoding decoding of error-correcting codes

Transient multiple cell upsets (MCUs) are beginning to seriously affect the reliability of memories when they are exposed to radiation settings. More complex error correction codes (ECCs) are often used to protect memory and prevent data corruption caused by MCUs; nevertheless, their primary drawback is an increase in delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory protection. The two error correction codes and the fact that not all situations lead to an improvement in mistake correction skills are the main issues. This work proposes a revolutionary decimal matrix code (DMC) based on the divide-symbol to provide better memory reliability with minimal delay overhead. The proposed DMC uses the decimal algorithm to provide the maximum amount of error detection capability. Furthermore, to minimize the area overhead of extra circuits without interfering with the encoding and decoding processes, it is advised to implement the encoder-reuse method (ERT)

Since its invention by McEliece in 1978, cryptography based on Error Correcting Codes (ECC) has suffered from the reputation of not being suitable for constrained devices. Indeed, McEliece's scheme and its variants have large public keys and relatively long ciphertexts. Recent works on these downsides explored the possible use of ECC based on rank metric instead of Hamming metric. These codes were introduced in the late 80's to eliminate errors with repeating patterns, regardless of their Hamming weight. Numerous proposals for the NIST Post-Quantum Cryptography (PQC) competition rely on these codes. It has been proven that lattice-based cryptography and even hash-based signatures can run on lightweight devices, but the question remains for code-based cryptography. In this work, we demonstrate that this is actually possible for rank metric: we have implemented the encryption operation of 5 schemes based on ECC in rank metric and made them run on an Arm Cortex-M0 processor, the smallest Arm processor available. We describe the technical difficulties of porting rank-based cryptography to a resource-constrained device while maintaining decent performance and a suitable level of security against side-channel attacks, especially timing attacks.

Resiliency will be one of the toughest challenges in future exascale systems. Memory errors contribute more than 40% of the total hardware-related failures and are projected to increase in future exascale systems. The use of error correction codes (ECC) and checkpointing are two effective approaches to fault tolerance. While there are numerous studies on ECC or checkpointing in isolation, this is the first paper to investigate the combined effect of both on overall system performance and power. Specifically, we study the impact of various ECC schemes (SECDED, BCH, and chip-kill) in conjunction with checkpointing on future exascale systems. Our simulation results show that while chipkill is 13% better for computation-intensive applications, BCH has a 28% advantage in system energy-delay product (EDP) for memory-intensive applications. We also propose to use BCH in tagged memory systems with commodity DRAMs where chipkill is impractical. Our proposed architecture achieves 2.3× better system EDP than state-of-the-art tagged memory systems.

It is now well known that using a long and complicated error correcting code (ECC) designed for the worst-case error probability requirement wastes excessive total system energy (transmit + circuit energy) when the error probability requirement is much higher than the worst case. We propose a novel adaptive polar coding strategy that adjusts the decoder circuit to consume minimal decoding circuit energy at each given target error requirement. By combining Thompson's VLSI theory and scaling analysis of polar codes, we provide upper bounds on energy, area, and time complexity of polar decoding circuits in terms of target block error probability. The upper bounds are derived from an explicit construction of decoder circuit based on mesh-network structure. Our comparison shows that the proposed energy-adaptive coding strategy has a scaling-sense gain in decoding energy with little circuit area overhead when there is a large gap between the worst-case and typical target error rate requirements.