An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory

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The continuous raise in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, computer memory is affected by Single Cell Upsets (SCU) and Multiple Cell Upsets (MCU). A common method to tolerate errors in this element is the use of Error Correction Codes (ECC). The addition of an ECC introduces a series of overheads: silicon area, power consumption and delay overheads of encoding and decoding circuits, as well as several extra bits added to allow detecting and/or correcting errors. ECC can be designed with different parameters in mind: low redundancy, low delay, error coverage, etc. The idea of this paper is to study the effects produced when adding an ECC to a microprocessor with respect to overheads. Usually, ECC with different characteristics are continuously proposed. However, a great quantity of these proposals only present the ECC, not showing its behavior when using them in a microprocessor. In this work, we present the design of an ECC whose main characteristic is a low number of code bits (low redundancy). Then, we study the overhead this ECC introduces. Firstly, we show a study of silicon area, delay and power consumption of encoder and decoder circuits, and secondly, how the addition of this ECC affects to a RISC microprocessor.

Multiple Cell Upsets (MCUs) induced by ionizing radiation in memories are becoming more likely to happen due to the continuous technology scaling down. Error Correction Codes (ECCs) are applied for recovering the stored information into its original state providing reliable computer systems. Several ECC are able to deal with MCUs, however, the higher the robustness of an ECC, more area, and energy is required for its implementation, becoming a problem if applied in application where resources are scarce. This article presents the implementation and evaluation of the Matrix Region Section Code (MRSC), a new algorithm for the detection and correction of multiple transient faults in volatile memories with low cost implementation. The experimental results measuring error coverage composed by detection and correction analysis, area, power and delay overheads have shown that MRSC is an excellent option to counteract with MCUs.

Soft errors have been a concern in memories for many years. In older technologies, soft errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets (MCUs) that affect a group of nearby cells have become more common. This trend is expected to continue making MCUs more frequent and also increasing the number of cells affected. To avoid data corruption in memories, Error Correction Codes (ECCs) are used. Single Error Correction (SEC) codes that can correct one bit error per word are effective only against single errors. To protect against MCUs, one option is to use more sophisticated error correction codes like for example, Orthogonal Latin Squares Codes (OLSC). In this paper, a modification of the OLSC decoding algorithm is proposed for codes that can correct two random errors. This modification has little impact on circuit complexity and enables triple adjacent error correction which is interesting when MCUs are present.

Due to vast integration density in CMOS technology, faults in the embedded or external memory have been increased. This manifests as single-cell upsets (SCU) and multiple cell upsets (MCU) for function, especially in flash memories. Flash memory provides far greater storage capacity at lower operating cost than SDRAM. Memories that operate in harsh environment like space can suffer from multiple errors. Due to the faults, data can be flipped from 1 to 0 or 0 to 1 or sometimes the message bits even get deleted. So, an embedded error correction code-based functional block is used along with dense memory, to ensure that the errors do not cause data corruption. This paper presents a method to protect memories from multiple cell upsets by adding redundancy. The error detection and correction can be done by using flexible unequal error control code (FUEC)-based design. The FUEC can detect and correct double, triple, and quadruple adjacent error. By using this method, low redundancy can be achieved in memory. The ECC engine was designed successfully, verified, and ready for integration to the memory. The design details are discussed below.

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

Transient multiple cell upsets (MCUs) are beginning to seriously affect the reliability of memories when they are exposed to radiation settings. More complex error correction codes (ECCs) are often used to protect memory and prevent data corruption caused by MCUs; nevertheless, their primary drawback is an increase in delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory protection. The two error correction codes and the fact that not all situations lead to an improvement in mistake correction skills are the main issues. This work proposes a revolutionary decimal matrix code (DMC) based on the divide-symbol to provide better memory reliability with minimal delay overhead. The proposed DMC uses the decimal algorithm to provide the maximum amount of error detection capability. Furthermore, to minimize the area overhead of extra circuits without interfering with the encoding and decoding processes, it is advised to implement the encoder-reuse method (ERT)

为了提高纠错编码（ECC）的有效性，先进的静态随机存储器（SRAM）多采用位交错结构。但是，在没有物理版图信息的情况下，位交错设计使得从辐照测试数据中提取出多单元翻转（MCU）变得更加困难。运用Bi离子辐照带有ECC的65 nm SRAM器件，研究了该款器件在重离子辐照下的敏感性。为伪多位翻转（FMBU）以及MCU的数据分析提供了理论指导和帮助，完善了判别MCU的基本法则。除此之外，研究结果表明，ECC的汉明编码对于纳米器件的效果不够理想。在未来的空间应用中，需考虑更高层次的编码算法来抵抗单粒子翻转。 In order to improve the robustness of error-correcting codes (ECC), modern static random access memory (SRAM) always use bit-interleaving structure. However, in the absence of physical layout information, the bit-interleaving design makes it more difficult to extract the multiple-cell upset (MCU) from the test data. In this paper, the sensitivity of Bi ion irradiation was investigated in a 65 nm technology SRAM with ECC. The experimental results provide a theoretical guidance and help for the fake multiple-bit upset (FMBU) and MCU data analyzing, which improve and perfect the basic rules extracting MCU from the test data. In addition, the results show that the performance of hamming encoding is not ideal in Nano scale SRAM. In the future of space applications, it is necessary to consider more advanced algorithms to against SEU.

Analysis of multiple cell upset characteristics for logical circuits in radiation environment

Circuit techniques for reducing the minimum supply voltage (V MIN ) of last-level and intermediate static random-access memory (SRAM) caches enhance processor energy efficiency. For the first time at a 16nm technology node, projections of a high-density 6-transistor SRAM bit cell indicate that the VMIN of a 4Mb or larger cache exceeds the maximum supply voltage (V MAX ) for reliability. Thus, circuit techniques for cache VMIN reduction are transitioning from an energy-efficient solution to a requirement for cache functionality. Traditionally, error-correcting codes (ECC) such as single-error correction, double-error detection (SECDED) aim to protect the cache operation from radiation-induced soft errors. Moreover, during the qualification of a system-on-chip (SoC) processor, test engineers monitor the rate of correctable cache errors from SECDED for observing the on-die interactions between integrated components (e.g., CPU, GPU, DSP, etc.). This presentation highlights the opportunity to exploit ECC for reducing the cache V MIN while simultaneously providing coverage for radiation-induced soft errors. Silicon test-chip measurements from a 7Mb data cache in a 20nm technology demonstrate a V MIN reduction of 19% from SECDED. In addition, silicon measurements provide a salient insight in that only 0.12% of the cache words contain an error when operating at the cache V MIN with SECDED. Therefore, SECDED improves V MIN by 19% while maintaining 99.88% coverage for radiation-induced soft errors. In applying SECDED for a lower cache VMIN, the rate of correctable errors exponentially increases, thus eliminating a useful metric for on-die observability. The presentation concludes by offering alternative solutions for on-die observability.

As technology scales, Multiple Cell Upsets (MCUs) become more common and affect a larger number of cells. In order to protect memories against MCUs as well as SEUs is to make use of advanced Error detecting and correcting codes that can correct more than one error per word. A sub-group of the low-density parity checks (LDPC) codes, which be-longs to the family of the Majority logic decoding has been recently proposed for memory application and Difference set codes are one example of these codes which contributes for error detection and correction. ML decodable Codes are suitable for memory applications due to their capability to correct a large number of errors. In this paper, the proposed scheme for fault-detection and correction method significantly makes area overhead minimal and to reduce the decoding time through DC codes than the existing technique and it gives promising option for memory applications. HDL implementation and synthesis results are included, showing that the proposed techniques can be efficiently implemented.

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit precomputation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weightcolumn code during the write operation and is designed by replacing 0’s with 1’s at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the oddweight-column code, the implementation based on the proposed SEC-DED code with check bit precomputation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

The significance of multiple cell upsets (MCUs) is revealed by sharing the soft-error test results in three major technologies, 90 nm, 65 nm, and 45 nm. The effectiveness of single-bit error correction (SEC) codes can be maximized in mitigating MCU errors when used together with the interleaving structure in memory designs. The model proposed in this paper provides failure probability to probabilistically demonstrate the benefits of various interleaving scheme selections for the memories with SEC. Grouped events such as MCU are taken into account in the proposed model by using the compound Poisson process. As a result of the proposed model, designers can perform predictive analysis of their design choices of interleaving schemes. The model successfully showed the difference in failure probability for different choices of interleaving schemes. The model behaved as the upper bound for failure probability when compared to the neutron test data with the 45-nm static-random-access memory (SRAM) design.

This paper presents measurement results of alpha-particle-induced soft errors and multiple cell upsets (MCUs) in 65-nm 10 T SRAM with a wide range of supply voltage from 1.0 V to 0.3 V. We reveal that the soft error rate (SER) at 0.3 V is eight times higher than SER at 1.0 V, and the ratio of MCUs to the total upsets increases as the supply voltage decreases. The SER and ratio of MCUs with body-biasing are also described. In addition, we investigate an impact of manufacturing variability on the soft error immunity of each memory cell. In our measurement, a distinct influence of manufacturing variability is not observed even in subthreshold region.

As the size of on-chip SRAM caches is increasing rapidly and the physical dimension of the SRAM devices is decreasing, reliability of caches is becoming a growing concern. This is because with increased size of caches, the likelihood of radiation-induced soft faults also increases. As a result, information redundancy in the form of Error Correcting Codes (ECC) is becoming extremely important, especially to protect the larger sized last level caches (LLCs). In typical ECCs, extra redundancy bits are added to every row to detect and correct errors. There is additional encoding (while writing data) and decoding (while reading data) procedures required as well. In caches, these additional area, power and latency overheads need to be minimized as much as possible. To address this problem, we present in this paper Parity++: a novel unequal message protection scheme for last level caches that preferentially provides stronger error protection to certain "special messages". This protection scheme provides Single Error Detection (SED) for all messages and Single Error Correction (SEC) for a subset of messages. Thus, it is stronger than just a basic SED parity and has much lower parity storage overhead (4X lower for a 64-bit memory) and lower error detection energy than a traditional Single Error Correcting, Double Error Detecting (SECDED) code. We also evaluate Parity++ with a memory speculation procedure that can be used with any ECC scheme to hide the decoding latency while reading messages when there are no errors.