SRAM Interleaving Distance Selection With a Soft Error Failure Model

为了提高纠错编码（ECC）的有效性，先进的静态随机存储器（SRAM）多采用位交错结构。但是，在没有物理版图信息的情况下，位交错设计使得从辐照测试数据中提取出多单元翻转（MCU）变得更加困难。运用Bi离子辐照带有ECC的65 nm SRAM器件，研究了该款器件在重离子辐照下的敏感性。为伪多位翻转（FMBU）以及MCU的数据分析提供了理论指导和帮助，完善了判别MCU的基本法则。除此之外，研究结果表明，ECC的汉明编码对于纳米器件的效果不够理想。在未来的空间应用中，需考虑更高层次的编码算法来抵抗单粒子翻转。 In order to improve the robustness of error-correcting codes (ECC), modern static random access memory (SRAM) always use bit-interleaving structure. However, in the absence of physical layout information, the bit-interleaving design makes it more difficult to extract the multiple-cell upset (MCU) from the test data. In this paper, the sensitivity of Bi ion irradiation was investigated in a 65 nm technology SRAM with ECC. The experimental results provide a theoretical guidance and help for the fake multiple-bit upset (FMBU) and MCU data analyzing, which improve and perfect the basic rules extracting MCU from the test data. In addition, the results show that the performance of hamming encoding is not ideal in Nano scale SRAM. In the future of space applications, it is necessary to consider more advanced algorithms to against SEU.

Multiple cell upsets (MCUs) become more and more problematic as the size of technology reaches or goes below 65 nm. The percentage of MCUs is reported significantly larger than that of single cell upsets (SCUs) in 20 nm technology. In SRAM and DRAM, MCUs are tackled by incorporating single-error correcting double-error detecting (SEC-DED) code and interleaved data columns. However, in content-addressable memory (CAM), column interleaving is not practically possible. A novel error correction code (ECC) scheme is proposed in this paper that will cater for ever-increasing MCUs. This work demonstrated that m parity bits are sufficient to cater for up to m-bit MCUs, with an understanding of the physical grouping of MCUs. The results showed that the proposed scheme requires 85% fewer parity bits compared to traditional Hamming distance based schemes.

Multiple Cell Upsets (MCUs) induced by ionizing radiation in memories are becoming more likely to happen due to the continuous technology scaling down. Error Correction Codes (ECCs) are applied for recovering the stored information into its original state providing reliable computer systems. Several ECC are able to deal with MCUs, however, the higher the robustness of an ECC, more area, and energy is required for its implementation, becoming a problem if applied in application where resources are scarce. This article presents the implementation and evaluation of the Matrix Region Section Code (MRSC), a new algorithm for the detection and correction of multiple transient faults in volatile memories with low cost implementation. The experimental results measuring error coverage composed by detection and correction analysis, area, power and delay overheads have shown that MRSC is an excellent option to counteract with MCUs.

Heavy ion-induced single event upsets (SEUs) of static random access memory (SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross sections and multiple cell upset (MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions. In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers (LETs). The average percentage of MCUs of 3D SRAM increases from 17.2 to 32.95%, followed by the energy of 209Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-to-face structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross sections of planar SRAM with experimental data. The upset cross sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields.

Due to the rapid growth of Internet of Things (IoT) devices such as smart appliances, health monitoring and surveillance systems, etc., there is a particular focus on memory design. The IoT connects devices to the internet to acquire information about the usage of sensors and embedded structures. Therefore, the ultimate aim is to reduce the average system energy and increase the battery life for IoT devices. IoT devices need to be portable, should consume less power and be light weight. These features provide the advantage of limiting the primary energy source to smaller batteries. Nowadays, ultra-low-power (ULP) systems on chip (SoCs) have extensively become chip makers’ choice. These SOCs require a low leakage memory architecture to operate at lower voltages with technology scaled devices. However, Static Random Access Memory (SRAM) design is challenging in scaled technology due to process and temperature variations that pose huge challenges in designing robust SoCs. Consequently, this chapter mainly focuses on the strategies to reduce the operating voltage of SRAM designed using FinFET technology and to enhance the battery life for ULP IoT devices.

Soft errors have been a concern in memories for many years. In older technologies, soft errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets (MCUs) that affect a group of nearby cells have become more common. This trend is expected to continue making MCUs more frequent and also increasing the number of cells affected. To avoid data corruption in memories, Error Correction Codes (ECCs) are used. Single Error Correction (SEC) codes that can correct one bit error per word are effective only against single errors. To protect against MCUs, one option is to use more sophisticated error correction codes like for example, Orthogonal Latin Squares Codes (OLSC). In this paper, a modification of the OLSC decoding algorithm is proposed for codes that can correct two random errors. This modification has little impact on circuit complexity and enables triple adjacent error correction which is interesting when MCUs are present.

Static Random Access Memory (SRAM) serves as a critical component in modern electronic devices, offering high-speed access to stored data. As technologycontinues to advance, there's a growing demand for smaller, faster, and more energy-efficient memory solutions. Carbon nanotubes (CNTs) have emerged as apromising material for pushing the boundaries of conventional silicon-based SRAM designs. This paper presents a comprehensive exploration of the design andoptimization of next- generation SRAM utilizing carbon nanotubes. The unique properties of CNTs, suchas their exceptional electrical conductivity, mechanical strength, and nanoscale dimensions, offer a fertile ground for revolutionizing SRAM architecture. The study delves into the integration of CNTs intoSRAM cell structures, discussing variousconfigurations and layouts to harness the advantageous characteristics of carbon nanotubes. Emphasis is placed on addressing the challenges associated with CNT-based SRAM, including manufacturing scalability, reliability, and variability. In conclusion, the integration of carbon nanotubesin SRAM design offers a compelling avenue to overcome the limitations of traditional silicon-based memory technologies. This study not only highlights the promising prospects of CNTs in SRAM but also provides insights into the challenges and opportunitiesin harnessing these nanomaterials for advanced memory applications. Keywords : Static Random Access Memory (SRAM), Carbon Nanotubes (CNTs), Nanotechnology, Memory Design, Optimization, Electronic Devices, Nanomaterial Integration.

The continuous raise in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, computer memory is affected by Single Cell Upsets (SCU) and Multiple Cell Upsets (MCU). A common method to tolerate errors in this element is the use of Error Correction Codes (ECC). The addition of an ECC introduces a series of overheads: silicon area, power consumption and delay overheads of encoding and decoding circuits, as well as several extra bits added to allow detecting and/or correcting errors. ECC can be designed with different parameters in mind: low redundancy, low delay, error coverage, etc. The idea of this paper is to study the effects produced when adding an ECC to a microprocessor with respect to overheads. Usually, ECC with different characteristics are continuously proposed. However, a great quantity of these proposals only present the ECC, not showing its behavior when using them in a microprocessor. In this work, we present the design of an ECC whose main characteristic is a low number of code bits (low redundancy). Then, we study the overhead this ECC introduces. Firstly, we show a study of silicon area, delay and power consumption of encoder and decoder circuits, and secondly, how the addition of this ECC affects to a RISC microprocessor.

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In this paper, single-event upset (SEU) is predicted using a combination of technology computer aided design (TCAD) and Geant4 Monte Carlo simulations. According to the layout topology of a 65 nm complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) arrays, the sensitive volumes (SVs) of off and on-transistors were calibrated by TCAD using novel circuit schematics. The effects of on-transistor charge collection on SEU were studied, and a novel criterion for SEU occurrence is proposed. Heavy ion simulation results indicate that the probability of SEU recovery increased with increased ion energy and striking tilt. The simulated SEU cross section and multiple cell upsets (MCUs) percentage based on the proposed method are in agreement with the experimental data for 6 T SRAM cells, which were fabricated using 65 nm processing technology.

Static random access memory (SRAM) product for advanced space applications must demonstrate high performance to meet the ever increasing data rates of space systems and must be radiation hardened to ensure unfettered, reliable operation in the harsh environments of outer space. High performance and radiation hardness are not mutually exclusive. The challenge confronting present day SRAM development is to concurrently achieve both of these objectives. An SRAM design evaluation methodology is described that uncovers limitations on performance, facilitating the identification of both the limiting mechanisms and the corrective design enhancements. Simulation model to hardware measurement correlation on two designs of radiation tolerant 4 M SRAM product validates the evaluation methodology. The evaluation methodology described herein can be Universally applied to any SRAM design to ensure that the highest performance potential of the design is realized.

Transient multiple cell upsets (MCUs) are beginning to seriously affect the reliability of memories when they are exposed to radiation settings. More complex error correction codes (ECCs) are often used to protect memory and prevent data corruption caused by MCUs; nevertheless, their primary drawback is an increase in delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory protection. The two error correction codes and the fact that not all situations lead to an improvement in mistake correction skills are the main issues. This work proposes a revolutionary decimal matrix code (DMC) based on the divide-symbol to provide better memory reliability with minimal delay overhead. The proposed DMC uses the decimal algorithm to provide the maximum amount of error detection capability. Furthermore, to minimize the area overhead of extra circuits without interfering with the encoding and decoding processes, it is advised to implement the encoder-reuse method (ERT)

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

A high-speed low-power novel architecture of Dual Bit Content Addressable Memory (DB-CAM) is reported in this article. A low leakage, low power and high-speed memory has been developed using the novel architecture of DB-CAM that can store 2 bits in a single CAM block and Static Random Access Memory (SRAM). Data search operation is done by using CAM cells and SRAMs are used as data storage cells. The output of SRAM cells depend on the search result of CAM cells. To make the search operation more precise a priority detector circuit has been proposed. The new architecture of DB-CAM block reduces the power consumption, transistor count and the area on chip enormously. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre (CADENCE) using standard 90 nm CMOS technology.

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode