Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

A low power CMOS Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGA) architecture is being presented in this paper. The architecture presented here is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. This architecture employs the fast and low-power SRAM blocks that are based on 10T SRAM cells. These blocks are employed in fast access of the configuration bits by using the shadow SRAM technique. The dynamic reconfiguration delay is being hidden behind the computation delay through the use of shadow SRAM cells. The combined effect of both the SRAM memory cells and the shadow SRAM scheme enables to support in reducing the delay and also to achieve reduced power consumption. Experimental results show reduced delay of about 8.035ns and power consumption of about 0.015W for the 10T SRAM memory cell with an overhead in area, relative to 4T and 6T SRAM cells. Also, the experimental results include the values of delay of about 8.979ns and power consumption of about 0.052W, achieved for the LB of FPGA architecture which employs CMOS SRAMs using the 10T SRAM memory cells in it.

为了提高纠错编码（ECC）的有效性，先进的静态随机存储器（SRAM）多采用位交错结构。但是，在没有物理版图信息的情况下，位交错设计使得从辐照测试数据中提取出多单元翻转（MCU）变得更加困难。运用Bi离子辐照带有ECC的65 nm SRAM器件，研究了该款器件在重离子辐照下的敏感性。为伪多位翻转（FMBU）以及MCU的数据分析提供了理论指导和帮助，完善了判别MCU的基本法则。除此之外，研究结果表明，ECC的汉明编码对于纳米器件的效果不够理想。在未来的空间应用中，需考虑更高层次的编码算法来抵抗单粒子翻转。 In order to improve the robustness of error-correcting codes (ECC), modern static random access memory (SRAM) always use bit-interleaving structure. However, in the absence of physical layout information, the bit-interleaving design makes it more difficult to extract the multiple-cell upset (MCU) from the test data. In this paper, the sensitivity of Bi ion irradiation was investigated in a 65 nm technology SRAM with ECC. The experimental results provide a theoretical guidance and help for the fake multiple-bit upset (FMBU) and MCU data analyzing, which improve and perfect the basic rules extracting MCU from the test data. In addition, the results show that the performance of hamming encoding is not ideal in Nano scale SRAM. In the future of space applications, it is necessary to consider more advanced algorithms to against SEU.

This paper presents measurement results of alpha-particle-induced soft errors and multiple cell upsets (MCUs) in 65-nm 10 T SRAM with a wide range of supply voltage from 1.0 V to 0.3 V. We reveal that the soft error rate (SER) at 0.3 V is eight times higher than SER at 1.0 V, and the ratio of MCUs to the total upsets increases as the supply voltage decreases. The SER and ratio of MCUs with body-biasing are also described. In addition, we investigate an impact of manufacturing variability on the soft error immunity of each memory cell. In our measurement, a distinct influence of manufacturing variability is not observed even in subthreshold region.

We have performed real-time soft error rate (SER) measurements on bulk 65 nm static random-access memories (SRAMs) during deuterium–deuterium (D-D) plasma operation at W–tungsten– Environment in Steady-state Tokamak (WEST). The present measurement campaign was characterized by the production of several tens of long pulse discharges (~60 s) and by a total neutron fluence (at the level of the circuits under test) up to ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> n.cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , improving the error statistics by a factor of more than 6 with respect to the first measurements obtained in 2020. Experimental results demonstrate the occurrence of bursts of single-event upsets (SEUs) during the most efficient shots and 12% of multiple cell upset (MCU) events. Time-resolved data also show that MCUs are preferentially detected in the last part of these long pulses, providing further evidence that higher energy neutrons, initiated by deuterium–tritium (D-T) reactions due to triton burn-up in the D-D plasma, may play a role in the production of multiple cell upsets that cannot be attributed in such large proportions to “low energy” neutrons produced in D-D reactions.

Heavy ion-induced single event upsets (SEUs) of static random access memory (SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross sections and multiple cell upset (MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions. In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers (LETs). The average percentage of MCUs of 3D SRAM increases from 17.2 to 32.95%, followed by the energy of 209Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-to-face structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross sections of planar SRAM with experimental data. The upset cross sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields.

This paper presents the design and analysis of a dynamically reconfigurable field programmable gate array (FPGA) that consists of three physical layers: routing and logic block layer, routing layer, and memory layer. The architecture was developed using a methodology that examines different architectural parameters and how they affect different performance criteria such as speed, area, and reconfiguration time. The resulting architecture has high performance while the requirement of balancing the areas of its constituent layers is satisfied.

Reconfigurable architectures possess the flexibility of software solutions as well as the high performance typified by hardware implementations to offer an excellent platform for developing quality-driven embedded applications. Among reconfigurable platforms, the dynamically Reconfigurable Field Programmable Gate Arrays (FPGAs) are most frequently employed for developing adaptive hardware software systems, so called Systems-on-Chip (SoC). For these systems to be fielded in harsh environments such as those encountered in space, extra-terrestrial locations and regions of extreme conditions on the earth, one must adopt fault tolerant design techniques to ensure uninterrupted and reliable operation despite the occurrence of faults. Commercial Off-the-Shelf (COTS) FPGA components offer a cost effective design trajectory where the designer can choose among a rich variety of FT approaches and techniques. Even though a large body of research has delved into the problem of fault tolerant design, there is a paucity of survey that indicates their applicability to FPGA-based SoC design. This paper attempts to categorize and compare the various FT techniques and discuss how they can work together to provide a synergetic approach for fault tolerant FPGA design.

Radiation-induced soft error rate (SER) degrades the reliability of static random access memory (SRAM)-based field programmable gate arrays (FPGAs). This paper presents a new built-in 2-D Hamming product code (2-D HPC) scheme to provide reliable operation of SRAM-based FPGAs in hostile operating environments such as space. Multibit error correction capability of our built-in 2-D HPC can improve the reliability, and hence, system availability, by orders of magnitude. Simulation results show that the large number of error correction capability of 2-D HPC can recover configuration bits without depending on an external memory preserving a golden copy of the configuration bits. To provide efficient 2-D HPC in a built-in logic, we also propose a new 2-D SRAM buffer. Using the proposed multibit error correction scheme, system availability of an SRAM-based FPGA can be more than 99.9999999% with SRAM cell failures in 1 billion h of operation of 7.

In this paper, single-event upset (SEU) is predicted using a combination of technology computer aided design (TCAD) and Geant4 Monte Carlo simulations. According to the layout topology of a 65 nm complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) arrays, the sensitive volumes (SVs) of off and on-transistors were calibrated by TCAD using novel circuit schematics. The effects of on-transistor charge collection on SEU were studied, and a novel criterion for SEU occurrence is proposed. Heavy ion simulation results indicate that the probability of SEU recovery increased with increased ion energy and striking tilt. The simulated SEU cross section and multiple cell upsets (MCUs) percentage based on the proposed method are in agreement with the experimental data for 6 T SRAM cells, which were fabricated using 65 nm processing technology.

On-board reconfiguration of FPGAs on a spacecraft offers the important advantage of allowing the reuse of the same hardware component for different functionalities during a mission. To be able to benefit from these features, a solution to cope with the challenges of using SRAMbased FPGAs in a radiation environment is required, and at the same time it is desired that the FPGA reconfiguration takes place at high speed. The BRAVE NG-MEDIUM FPGA offers a solution for this problem, by combining being radiation-hardened by design and reconfiguration of the programmable logic via a high-speed communication protocol, namely SpaceWire. In this paper we compare the performance of SpaceWire with Joint Test Action Group (JTAG) for NG-MEDIUM reconfiguration, in terms of the time elapsed when uploading a bitstream file from a Central Processing Unit (in our case from a computer) to the Field Programmable Gate Array (FPGA) and the time needed for uploading such bitstream and configuring the FPGA with the uploaded bitstream.

Field Programmable Gate Array (FPGA) has been widely adopted as modern reconfigurable computing platforms. Traditionally, the storage elements in FPGAs are static RAM (SRAM), which has large leakage power and limited scalability. Recently, non-volatile memory (NVM) is proposed to replace the SRAM in FPGA systems for static power and density considerations, at the cost of inducing larger dynamic power. Hybrid FPGAs combine the advantages of SRAM and NVM by employing both SRAM and NVM as logic storage elements. Although the feasibility of hybrid FPGA has been confirmed, the design flow has not fully explored the hybrid features yet, resulting in inferior system performance. Besides, traditional design flow does not consider the reconfiguration cost, which may prolong the reconfiguration procedures and thus degrade the system performance in dynamically reconfigurable FPGA systems. This work proposes a runtime and reconfiguration dual aware placement strategy for dynamically reconfigurable hybrid architecture. The proposed scheme considers the tradeoff between runtime and dynamic reconfiguration latency and optimizes the overall performance of the reconfigurable system. Evaluation shows that the proposed scheme improves the system performance by 14.6% for SRAM-MRAM hybrid FPGAs compared with the default placement strategy.

Due to vast integration density in CMOS technology, faults in the embedded or external memory have been increased. This manifests as single-cell upsets (SCU) and multiple cell upsets (MCU) for function, especially in flash memories. Flash memory provides far greater storage capacity at lower operating cost than SDRAM. Memories that operate in harsh environment like space can suffer from multiple errors. Due to the faults, data can be flipped from 1 to 0 or 0 to 1 or sometimes the message bits even get deleted. So, an embedded error correction code-based functional block is used along with dense memory, to ensure that the errors do not cause data corruption. This paper presents a method to protect memories from multiple cell upsets by adding redundancy. The error detection and correction can be done by using flexible unequal error control code (FUEC)-based design. The FUEC can detect and correct double, triple, and quadruple adjacent error. By using this method, low redundancy can be achieved in memory. The ECC engine was designed successfully, verified, and ready for integration to the memory. The design details are discussed below.

The emerging reconfigurable computing reduces the need of computation exhaustive applications, which are always demanding more efficient computation hardware. The partially reconfigurable Field Programmable Gate Arrays (FPGA) are highly suitable for performance improvement. This paper discusses the study of FPGA utilization when scheduling fixed size configurable computation hardware block (CCHB) by applying a heuristic. Based on the parameters (speedup, CCHB size etc.,) associated with the independent CCHBs, scheduling is performed and it is repeated for various sizes of FPGA. From the study of four applications from benchmark suite, it is observed that the device utilization is increased with size of CCHBs not greater than 0.5 times or not less than 0.85 times of the size of FPGA.

We characterize soft errors of SRAM devices fabricated over a range of technology nodes and show that both single-bit upsets (SBUs) and multiple-cell upsets (MCUs) decrease with technology scaling. Implementation of FinFET transistors leads to a significant reduction in both SBUs and MCUs relative to planar transistors. We find the mechanisms responsible for SBU and MCU events are unaffected by the transition to the FinFET architecture. For errors due to alpha particles and thermal neutrons, the relative occurrence of single event upsets is determined primarily by the sensitive area of the drain of bit cell transistors. We show that high-energy neutron-induced MCU events are determined by charge sharing among adjacent cells and are sensitive to both transistor drain area and the details of the process technology (i.e., manufacturing sequence) used, via the dependence of charge mobility on the substrate doping level.

Recent advances in intelligence technology have boosted the development of micro- Unmanned Air Vehicles (UAVs) including Sliver Fox, Shadow, and Scan Eagle for various surveillance and reconnaissance applications. These affordable and reusable devices have to fit a series of size, weight, and power constraints. Cameras used on such micro-UAVs are therefore mounted directly at a fixed angle without any motion-compensated gimbals. This mounting scheme has resulted in the so-called <i>jitter effect</i> in which jitter is defined as sub-pixel or small amplitude vibrations. The jitter blur caused by the jitter effect needs to be corrected before any other processing algorithms can be practically applied. Jitter restoration has been solved by various optimization techniques, including Wiener approximation, maximum <i>a-posteriori</i> probability (MAP), etc. However, these algorithms normally assume a spatial-invariant blur model that is not the case with jitter blur. Szu et al. developed a smart real-time algorithm based on auto-regression (AR) with its natural generalization of unsupervised artificial neural network (ANN) learning to achieve restoration accuracy at the sub-pixel level. This algorithm resembles the capability of the human visual system, in which an agreement between the pair of eyes indicates "signal", otherwise, the jitter noise. Using this non-statistical method, for each single pixel, a deterministic blind sources separation (BSS) process can then be carried out independently based on a deterministic minimum of the Helmholtz free energy with a generalization of Shannon's information theory applied to open dynamic systems. From a hardware implementation point of view, the process of jitter restoration of an image using Szu's algorithm can be optimized by pixel-based parallelization. In our previous work, a parallelly structured independent component analysis (ICA) algorithm has been implemented on both Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) using standard-height cells. ICA is an algorithm that can solve BSS problems by carrying out the all-order statistical, decorrelation-based transforms, in which an assumption that neighborhood pixels share the same but unknown mixing matrix <b>A</b> is made. In this paper, we continue our investigation on the design challenges of firmware approaches to smart algorithms. We think two levels of parallelization can be explored, including pixel-based parallelization and the parallelization of the restoration algorithm performed at each pixel. This paper focuses on the latter and we use ICA as an example to explain the design and implementation methods. It is well known that the capacity constraints of single FPGA have limited the implementation of many complex algorithms including ICA. Using the reconfigurability of FPGA, we show, in this paper, how to manipulate the FPGA-based system to provide extra computing power for the parallelized ICA algorithm with limited FPGA resources. The synthesis aiming at the pilchard re-configurable FPGA platform is reported. The pilchard board is embedded with single Xilinx VIRTEX 1000E FPGA and transfers data directly to CPU on the 64-bit memory bus at the maximum frequency of 133MHz. Both the feasibility performance evaluations and experimental results validate the effectiveness and practicality of this synthesis, which can be extended to the spatial-variant jitter restoration for micro-UAV deployment.