System implications of memory reliability in exascale computing

Error-Correcting Code (ECC) provides robust readability to both linear and two-dimensional (2D) barcodes, particularly for localized damage. Many ECC approaches, however, are based on assumptions about the types of damage or the communication channel used. As the applications for barcodes rapidly evolve with the increasing ubiquity of mobile cameras, an evaluation of the trade off between ECC and simply increasing the size of the bar code modules is required. This article compares the impact of simply changing the module size versus using error correction–which exhausts a percentage of the symbol area without adding payload data. For three typical nondestructive types of damage–the print-scan cycle, low quality printing, and blurring–investigated here, there is compelling support for increasing the size of the barcode modules and foregoing ECC. Freeing barcodes from the need for ECC provides an additional advantage: namely, the barcodes can be scrambled to be unreadable under the defined barcode specification without a change in size or appearance. This is in contrast to the use of ECC, for which only a small minority of rearrangements of the data in the barcode would be "decodable." Thus, without the use of ECC, it is much harder for a would-be counterfeiter or other dishonest party to determine the scrambling approach. Additionally, we can create 2D barcodes that are not "readable" using commercially available reading software, except where so desired. These results are discussed in light of destructive damage and for different applications of 2D bar codes.

The continuous raise in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, computer memory is affected by Single Cell Upsets (SCU) and Multiple Cell Upsets (MCU). A common method to tolerate errors in this element is the use of Error Correction Codes (ECC). The addition of an ECC introduces a series of overheads: silicon area, power consumption and delay overheads of encoding and decoding circuits, as well as several extra bits added to allow detecting and/or correcting errors. ECC can be designed with different parameters in mind: low redundancy, low delay, error coverage, etc. The idea of this paper is to study the effects produced when adding an ECC to a microprocessor with respect to overheads. Usually, ECC with different characteristics are continuously proposed. However, a great quantity of these proposals only present the ECC, not showing its behavior when using them in a microprocessor. In this work, we present the design of an ECC whose main characteristic is a low number of code bits (low redundancy). Then, we study the overhead this ECC introduces. Firstly, we show a study of silicon area, delay and power consumption of encoder and decoder circuits, and secondly, how the addition of this ECC affects to a RISC microprocessor.

A serial peripheral interface (SPI) 16-Kbit phase change memory chip based on 0.13μm CMOS process is designed. It contains a parallel error correcting code (ECC) circuit, which can correct 2 bits in every 8 bits without clock delay, enabling the write and read operations performed at bus speed. All the data transfers in 8-bit groups and can be read or written with write protection scheme by unlimited cycle, in which address can automatically increase one by one. Simulation results show that the chip can work correctly in SPI mode and with ECC scheme. It is now under testing.

Technology advances have recently enabled the use of DRAMs into logic integrated circuits. These embedded DRAMs can be used to efficiently implement caches since DRAMs require substantially less area than SRAMs. One challenge for DRAM based caches is that a small time between refreshes is needed to ensure data retention. These refreshes increase the power consumption even when the cache is idle. To mitigate this issue, the use of longer times between refreshes combined with the use of Error Correction Codes (ECCs) has been recently proposed. The idea is that the time between refreshes can be increased significantly while only causing data retention failures on a small percentage of the cells. Then those errors can be corrected by the ECC. For this scheme to be efficient the number of additional bits required by the ECC should be small. This is achieved by using large data blocks for the ECC which in turns means that a large data block has to be accessed even when only a small portion of it is needed. This has no effect on idle power consumption but increases the dynamic power consumption and reduces the effective memory bandwidth. In this paper, a technique to mitigate this issue is proposed. It enables better granularity in the read data accesses by partitioning the ECC block into two sub-blocks and modifying the error detection and correction processes. This reduces the dynamic power consumption and increases the available memory bandwidth while requiring only a moderate increase in the number of additional bits.

Three-dimensional (3D) error correction coding (ECC) provides volumetrically coupled ECC blocks, the possible errors of which can be controlled powerfully by correcting errors from three different directions, iteratively. However, increased parities cause a large overhead, which limits the application of strong ECC schemes. In this study, a new efficient 3D ECC scheme and its decoding algorithm for holographic data storage were developed and evaluated. The proposed scheme has 3D ECC capability with a relatively low coding overhead, similarly to that of conventional 2D error correcting schemes, such as RSPC. It gives favorable ECC performance with a high efficiency in a page-based recording and retrieving system, which enables the use of a 3D ECC scheme for various applications.

Considering the insatiable demand for high-performance computing, on-chip cache capacity increases rapidly. Spin-transfer-torque magnetoresistive random-access memory (STT-MRAM) is a promising cache candidate due to ultralow standby power, high-access speed, and integration density. Unfortunately, when the feature size of magnetic tunnel junction (MTJ) scales down to 1 Xnm, read current approaches write current closely, which may result in read disturbance threatening the reliability of STT-MRAM. Furthermore, the elevating on-chip temperature reduces the thermal stability of STT-MRAM remarkably and aggravates the read disturbance. Error correction code (ECC) is an effective technique to enhance memory reliability. In this paper, we take advantage of the thermal dependence of STT-MRAM and propose a thermally adaptive ECC design, called “Chameleon,” that can adjust the ECC protection strength dynamically to reduce the ECC storage overhead and improve the cache access performance and energy efficiency. Experimental results show that compared to the conservative nonadaptive ECC scheme, our design can improve both cache performance and energy consumption effectively.

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Since its invention by McEliece in 1978, cryptography based on Error Correcting Codes (ECC) has suffered from the reputation of not being suitable for constrained devices. Indeed, McEliece's scheme and its variants have large public keys and relatively long ciphertexts. Recent works on these downsides explored the possible use of ECC based on rank metric instead of Hamming metric. These codes were introduced in the late 80's to eliminate errors with repeating patterns, regardless of their Hamming weight. Numerous proposals for the NIST Post-Quantum Cryptography (PQC) competition rely on these codes. It has been proven that lattice-based cryptography and even hash-based signatures can run on lightweight devices, but the question remains for code-based cryptography. In this work, we demonstrate that this is actually possible for rank metric: we have implemented the encryption operation of 5 schemes based on ECC in rank metric and made them run on an Arm Cortex-M0 processor, the smallest Arm processor available. We describe the technical difficulties of porting rank-based cryptography to a resource-constrained device while maintaining decent performance and a suitable level of security against side-channel attacks, especially timing attacks.

In Ultra Deep Sub Micron (UDSM) Technology, accomplishment of error free data transmission through Network on Chip (NoC) interconnect becomes impractical. This difficult state is widely managed by the use of Error Correction Codes (ECC) in NoC. A novel Hamming based Multiple Transient Error Correction (HMTEC) code is proposed to enhance the NoC interconnect reliability. Implementation of this code corrects all single bit errors and most of the combinations of errors upto 8 bits for a flit size of 32. Furthermore, this code allows error correction in both data and redundant bits. This coding method is performed at lower power consumption, area occupancy and delay when measured against similar codes proposed in recent years.

Current trends in exascale systems research indicate that heterogeneity will abound in both the hardware and software layers on future HPC systems. It is our position that exascale environments are likely to be constructed from independent partitions of hardware and system software called enclaves, with multiple enclaves co-located on the same physical nodes and each executing an optimized operating system and runtime (OS/R) to support a particular application behavior. Fully utilizing these systems will require the ability to execute composed workloads, such as in situ applications, whereby HPC simulations execute synchronously with co-located analytic packages that in turn process simulation output via shared memory. In this work, we present the design and implementation of XEMEM, a shared memory system that can efficiently construct memory mappings across enclave OSes to support composed workloads while allowing diverse application components to execute in strictly isolated enclaves. By utilizing modifications to the Kitten lightweight kernel and Palacios lightweight virtual machine monitor, as well as leveraging our recent work on lightweight co-kernels, we demonstrate that our approach can support a diverse range of native and virtualized environments likely to be deployed on future exascale systems. Finally, we demonstrate that a multi-enclave system can reduce cross-workload contention and improve performance for a sample composed benchmark compared to a single OS approach.

The conventional error correcting code (ECC) schemes for caches are based on a fixed mapping between cache data words and ECC check bits, and fixed ECC word granularity. This leads to inefficient usage of the ECC check bits. We propose to manage the check bits flexibly for low-cost error protection of last-level caches. The proposed ECC schemes work at the word level, whereas the conventional ECC schemes work at the cache line or set level. The proposed schemes protect only dirty words with ECC check bits using a flexible mapping. Moreover, the proposed schemes utilize variable ECC word granularities. Dirty (modified) words that are unlikely to be modified further before being evicted are collectively protected with a larger ECC word granularity. The proposed schemes reduce DRAM and data bus energy overheads by 28% and 45%, respectively, with the same area overhead as previously proposed competitive schemes. Our schemes show more energy reduction results for multicore systems without noticeable performance degradation.

Objectives. Programmable logic integrated circuits of the field programmable gate array (FPGA) type based on static configuration memory are widely used in the electronics of onboard spacecraft systems. Under the influence of space radiation, errors may occur in the FPGA configuration memory. The main methods of protection against such errors involve various options for reservation triggers, as well as the use of error-correcting codes in special error detection and correction circuits. The purpose of the present work is to determine which error-correcting codes are best suited to the implementation of internal scrubbing of the FPGA configuration memory taking redundancy into account.Methods. The paper analyses various methods for scrubbing FPGA configuration memory, which are used to correct errors caused by the action of space radiation. It is proposed to increase the efficiency of internal scrubbing of the FPGA configuration memory using codes that correct both single- and double-adjacent SEC-DED-DAEC errors. In this case, the need to perform external scrubbing of the configuration memory is reduced by overwriting it with a reference configuration from non-volatile radiation-resistant memory; in this way, FPGA downtime caused by the external scrubbing procedure is reduced. Due to the known SEC-DED-DAEC codes having a non-zero probability of erroneous detection and subsequent erroneous correction of a double non-adjacent error, as well as various redundancy and implementation complexities, a study was made of the most efficient code for internal scrubbing.Results. The results showed that the Datta, Neale and Hoyoon–Yongsurk codes are optimal from the indicated positions. Recommendations are given for selecting a specific code depending on the specific requirements for a particular planned space mission.Conclusions. The study confirms the effectiveness of protecting the memory of programmable logic by using two-error-correcting codes.

Massively heterogeneous architectures are popular for modern petascale and future exascale systems. Fault-tolerance is key to the increased number of components and the complexity of these heterogeneous systems. However, standard offload programming models have traditionally been developed for supporting high performance rather than reliability. Naive fault-tolerance protocols are incapable of serving distributed MPI applications that tuned for CPU-MIC heterogeneous clusters. To address these problems, we design and implement a framework of fault tolerance programming model (FT-Offload). This enhances the reliability of heterogeneous supercomputers and retains the convenient of popular Intel Offload programming model. The effectiveness of the framework is demonstrated via numerical analysis and by porting both benchmarks and real-world applications to large-scale CPU-MIC nodes on the Tianhe-2 supercomputer. Our experimental results show that the current solution, which involves checkpoints, can efficiently strength the long running and reduce checkpointing overhead.

Petascale simulations have become mission critical in diverse areas of science and engineering. Knowledge discovery from such simulations remains a major challenge and is becoming more urgent as the march towards ultra-scale computing with millions of cores continues. One major issue with the current paradigm of running the simulations and saving the data to disk for post-processing is that it is only feasible to save the data at a small number of time slices. This low temporal resolution of the saved data is a serious handicap in many studies where the time evolution of the system is of principle interest. One way to address this I/O issue is through in-situ visualization strategies. The idea is to minimize data storage by extracting important features of the data and saving them, rather than raw data, at high temporal resolution. Parallel file systems of current petascale and future exascale systems are expensive shared resources and need to be utilized effectively, and similarly archival storage can be limited and both of these will benefit from in-situ visualization as it will lead to intelligent way of utilizing storage. In this paper, we present preliminary results from our in-situ visualization for global hybrid (electron fluid, kinetic ions) simulations which are used to study the interaction of the solar wind with planetary magnetospheres such as the Earth and Mercury. In particular, we examine the overhead and effect on code performance associated with the inline computations associated with in-situ visualization.

To meet the expected performance, future exascale systems will require programmers to increase the level of parallelism of their applications. Novel programming models simplify parallel programming at the cost of increasing runtime overheard. Assisted execution models have the potential of reducing this overhead but they generally also reduce processor utilization.We propose an integrated hardware/software solution that automatically partition hardware resources between application and auxiliary threads. Each system level performs well-defined tasks efficiently: 1) the runtime system is enriched with a mechanism that automatically detects computing power requirements of running threads and drives the hardware actuators; 2) the hardware enforces dynamic resource partitioning; 3) the operating system provides an efficient interface between the runtime system and the hardware resource allocation mechanism. As a test case, we apply this adaptive approach to STM2, an software transactional memory system that implements the assisted execution model.We evaluate the proposed adaptive solution on an IBM POWER7 system using Eigenbench and STAMP benchmark suite. Results show that our approach performs equal or better than the original STM2 and achieves up to 65% and 86% performance improvement for Eigenbench and STAMP applications, respectively.