Realization of Multiple Valued Logic and Memory by Hybrid SETMOS Architecture

In modern technology era, the demand for Static Random Access Memory (SRAM) cells has been greatly increased due to its wide variety of applications. Power consumption, speed, read stability and leakage issues are the major design challenges related to SRAM. This paper presents a novel SRAM cell based on Multiple Supply Voltages and non-precharged RBL (MS-N10T) and also shows the comparison of various SRAM cells based on lector, sleep transistors and Transmission gate (TG) to reduce the power consumption when compared to LP10T. The SRAM cell MS-N10T when used in combination of TG and sleep transistors (TGNS-13T) further reduces the power consumption. The analysis further shows that the SRAM, TGNS13T reduces the power consumption approximately by 70-80%. On the Other hand, the LC14T SRAM cell enhances the stability approximately by 80-85%. The major objective of this work is to reduce the power consumption with marginal increase in propagation delay and to improve read stability so as to meet the challenges of advancements in technologies. All the various SRAM architectures are implemented using Cadence 45nm CMOS technology.  Â

This research paper proposes a low-power, high-stability 8T static random access memory (SRAM) cell. The proposed SRAM cell is a modified structure of the conventional 6T SRAM cell. The introduction of two diode-connected transistors in the pull-down network of the conventional 6T SRAM cell gives the proposed 8T SRAM cell structure. The presence of diode-connected transistors improves the power and noise performances of the proposed cell as compared to those of the conventional bit cells. The power consumption and static noise margin (SNM) of the suggested SRAM cell are calculated for write, hold and read operations. Also, the write and read delays of the proposed and conventional bit cells are observed. The power, speed, noise margin and area of the proposed 8T SRAM cell are compared with those of some of the existing SRAM cells. In comparison to conventional SRAM cells, the proposed cell consumes less power and has higher stability, according to the study. A novel dual-supply ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V or 200[Formula: see text]mV) concept is applied for the existing and proposed SRAM cells. The noise and power performances of SRAM cells are well improved under the condition of dual supply as compared to the conventional supply voltage ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V). A [Formula: see text] memory array of the proposed 8T SRAM cell is formed and the performance of the array structure is compared with that of [Formula: see text] array of the conventional 6T SRAM cell. The layouts of existing and proposed SRAM cells are illustrated. The simulation is carried out using the Cadence Virtuoso simulation EDA tool in 90-nm CMOS technology.

Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

As is known in the art, it is relatively difficult to write a logic ‘1’ to the five-transistor (5T) static random access memory (SRAM) cell if the SRAM cell currently stores a logic ‘0’. In this paper, we proposed a 5T SRAM cell and a cell voltage control circuit coupled to provide power to the SRAM cell. The cell voltage control circuit supplies the SRAM cell with the HVDD supply voltage if the SRAM cell is in a read mode. If the SRAM cell is being written or during a standby mode, the cell voltage control circuit supplies the SRAM cell with the LVDD supply voltage that is less than the HVDD supply voltage. Several HSPICE simulations show that the proposed SRAM cell provides an improvement in SRAM cell topology by providing an efficient solution to the write ‘1’ issue.

Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time ( ${T_{\mathrm{RA}}}$ ), and write access time ( ${T_{\mathrm{ WA}}} $ ) are also presented. The proposed cell achieves ${1.12{\times } /{\mathrm{ 1}}.{\mathrm{ 43}}{\times } /{\mathrm{ 5}}.{\mathrm{ 62}}\times } $ improvement in ${T_{\mathrm {RA}}}$ compared to TG8T/D6T/SE8T at a penalty of $ {1.1{\times } /{4}.{88}\times }$ in $ {T_{\mathrm{ WA}}} $ compared to D6T/TG8T and $ {1.19{\times } /1.18\times } $ in read/write power consumption compared to D6T. An improvement of $ {\rm 1.{\mathrm{ 12}}{\times } /{\mathrm{ 2}}.{\mathrm{ 15}}\times } $ in RSNM is observed compared to D6T/TG8T. The proposed cell consumes $ {5.38\times } $ less power during hold mode and also shows ${2.33\times } $ narrower spread in hold power @ $ {V_{\mathrm{ DD}} = 0.{\mathrm{ 4}}}$ V compared to D6T SRAM cell.

<p>In Very Large Scale Integration (VLSI) design, device scaling is restricted due to subthreshold swing limitations and short channel effects. This article discusses the role of different power reduction techniques in the implementation of 14 nm fin-shaped field-effect transistor (FinFET) centered static random access memory (SRAM) cells with good subthreshold swing and reduced short channel effects (SCE). Dynamic threshold and power gating are incorporated in SRAM cells to advance the memory cell performance by reducing static power dissipation in standby mode. The power analysis was performed on different SRAM cells with different transistor count i.e., 6, 7, 8, and 9. The performance of SRAM cell is analysed in power dissipation and is reduced by 20% using power gating method and in dynamic threshold it is reduced to nano watts due to less leakage power.</p>

Periodic drain current-gate voltage characteristics of single-electron transistors (SETs) were utilized to construct basic components of multiple-valued logic (MVL), such as a universal literal gate and a quantizer. In order to supplement the small gain and the small applicable voltage of the SET, hybrid SET-MOSFET scheme is proposed and demonstrated experimentally using CMOS-compatible pattern-dependent oxidation (PADOX) technology. We also succeeded in reproducing the results using a SPICE circuit simulator with a compact analytical SET model, and estimated the performance of the proposed MVL.

In this paper, we propose a radiation-tolerant by design 12 transistor (RTBD 12T) based Static Random Access Memory (SRAM) cell for deep space application. The designed SRAM cell can effectively tolerate radiation events. It exhibits high resilience towards radiation upsets and accordingly three out of four nodes of the cell are fully immune to radiation upsets, and it has a critical charge (QC) equal to 1.6 fC making it a more promising choice for deep space application. The design metrics of the proposed SRAM cell are compared with a few conventionally used SRAM cells like 6T, Quad node (QUATRO 10T) SRAM, Quadruple cross coupled storage cells (QUCCE 12T) and Writability Enhanced (WEQUATRO). The higher read stability is validated by the read static noise margin (RSNM) analysis in which the proposed cell achieves higher noise margin as compared to other SRAM cells. The proposed 12TSRAM cell exhibits improved results in terms of hold power, which is $\left( {0.86 \times } \right),\left( {0.40 \times } \right)$ and $\left( {0.74 \times } \right)$ compared to that of QUATRO 10T, QUCCE 12T and WEQUATRO, respectively.

This article presents a comprehensive assessment on the 6T static random access memory (SRAM) cell with 7-nm FinFET technology by implementing quantum physics-based device-circuit cooptimization. Seven key device design parameters and their multiple impacts on a 6T SRAM cell are systematically evaluated, focusing on materials band engineering, device design, circuit parameters tradeoff, and variation control. The area of SRAM cell under the same Fin quantization scheme remains constant in all evaluations. To the best of our knowledge, the most comprehensive discussion about circuit optimization from multiple device design parameters perspective is presented. Based on our cooptimization scheme, a SRAM cell is effectively designed. For a low-power and robust SRAM cell design, we achieve 56.7% reduction in leakage, 7.9% improvement in hold noise margin (HNM), 8.6% improvement in read noise margin (RNM), and 10.8% improvement in write margin (WM) at the expense of 19.3% increase in delay under design space of gate length (Lg) and spacer thickness (TSPC). For a high-speed SRAM cell design, we recommend focusing on the optimization of architecture and peripheral circuits. This framework not only has the advantages of easy implementation, technology-friendly, and high accuracy, but also suitable for path-finding researches on 5-nm node and beyond.

A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access time

A multipeak negative-differential-resistance(NDR) device which comprises a singl e-electron transistor (SET) and a metal-oxide-semiconductor field-effect-transis tor (MOSFET) can achieve infinite number of peaks in principle. The MOS device e liminates the large SD voltage dependence of the peak and volley currents of the SET. The multipeak NDR device can be widely used in multiple-valued logics, and analog-to-digital converters (ADCs). We obtain a multiple-valued memory unit th rough the multipeak NDR device. And by using the folding I-V characteristic, a four-bit ADC is achieved. Compared with the traditional flash ADC, the SET-MO SFET ADC is very simple.

SummaryDriven by technologies such as machine learning, artificial intelligence, and internet of things, the energy efficiency and throughput limitations of the von Neumann architecture are becoming more and more serious. As a new type of computer architecture, computing-in-memory is an alternative approach to alleviate the von Neumann bottleneck. Here, we have demonstrated two kinds of computing-in-memory designs based on two-surface-channel MoS2 transistors: symmetrical 4T2R Static Random-Access Memory (SRAM) cell and skewed 3T3R SRAM cell, where the symmetrical SRAM cell can realize in-memory XNOR/XOR computations and the skewed SRAM cell can achieve in-memory NAND/NOR computations. Furthermore, since both the memory and computing units are based on two-surface-channel transistors with high area efficiency, the two proposed computing-in-memory SRAM cells consume fewer transistors, suggesting a potential application in highly area-efficient and multifunctional computing chips.

A study of an eight-transistor static random access memory (SRAM) cell and its implementation in carbon nanotube FET (CNTFET) technology are presented. Simulations of the CNTFET SRAM cell design, using a CNT SPICE model, have shown advantages over the CMOS cell in terms of static power, dynamic power, and noise margin. However, current CNT synthesis processes grow metallic CNTs alongside semiconductor CNTs. This in turn greatly degrades the performance and functionality of SRAM cells. In this paper, we present and compare two approaches to overcome the presence of metallic CNTs. The first approach tolerates metallic CNTs and uses a series of uncorrelated CNTs to form a transistor; this provides tolerance to metallic CNTs. The second approach uses an M × N array of uncorrelated CNTs to form a CNTFET and requires technologies capable of removing metallic CNTs. Both approaches have similar static noise margin. The second approach (removed metallic CNTs) consumes 1.45× more static power; on the other hand, its CNT count and write delay are reduced to 35.6% and 10.9% of the metallic tolerant approach, respectively. The realization of large memory modules in the presence of faulty SRAM cells can be achieved by having memory modules with as few as two spare columns.

We present a hybrid nanoelectromechanical (NEM)/CMOS static random access memory (SRAM) cell, in which the two pull-down transistors of a conventional CMOS six transistor (6T) SRAM cell are replaced with NEM relays. This SRAM cell utilizes the infinite subthreshold slope and hysteretic properties of NEM relays to dramatically increase the cell stability compared to the conventional CMOS 6T SRAM cells. It also utilizes the zero off-state leakage of NEM relays to significantly decrease static power dissipation. The structure is designed so that the relatively long mechanical delay of the NEM relays does not result in performance degradation. Circuit simulations are performed using a VerilogA model of a NEM relay. Compared to a 65nm CMOS 6T SRAM cell, when 10nm-gap NEM relays (pull-in voltage = 0.8V, pull-out voltage = 0.2V, on resistance = 1ki2) are integrated, hold and read static noise margin (SNM) improve by ~110% and ~250%, respectively. In addition, static power dissipation decreases by ~85%. The write delay decreases by ~60%, while read delay decreases by ~10%. The advantages in SNM and static power dissipation are expected to increase with scaling.

The growing demand for low-power static random access memory (SRAM) cells in Internet of Things (IoT) devices has led to the development of various SRAM cell topologies that minimize power consumption while maintaining performance and stability. In this paper, we have analyzed various SRAM designs based on different parameters, such as power dissipation, delay, area, energy, and stability. It is observed that 6T SRAM cell, consisting of six transistors, is the most widely used topology due to its simplicity and low area requirements. However, larger cells such as 8T,9T, and 10T have been developed to improve stability and reduce power consumption, although they require more area. It has been observed8 T work better for read delay while 9T works better for 9 Scaling down SRAM cells to smaller feature sizes presents challenges in maintaining stability and reliability while minimizing power consumption.