Reconfigurable continuous Class-F power amplifier using tunable output matching network

Improvement of power amplifier’s performance is the desired topic in communication systems. There are many efforts are made to provide good input and output matching, high efficiency, sufficient power gain and appropriate output power. This paper presents a power amplifier with optimized input and output matching networks. In the proposed approach, a new structure of the Hidden Markov Model with 20 hidden states is used for modeling the power amplifier. The widths and lengths of the microstrip lines in the input and output matching networks are defined as the parameters that the Hidden Markov Model should optimize. For validating our algorithm, a power amplifier has been realized based on a 10W GaN HEMT with part number CG2H40010F from the Cree corporation. Measurement results have shown a PAE higher than 50%, a Gain of about 14 dB, and input and output return losses lower than -10 dB over the frequency range of 1.8–2.5 GHz. The proposed PA can be used in wireless applications such as radar systems.

Developments within modern nonlinear measurement systems offer an increasing degree of flexibility to the microwave power amplifier (PA) designer. The PA designer has historically been a driving factor in setting the development directions of new measurement systems, fueling the paradigm, that PA innovations largely push new measurement requirements. It would appear that measurement system manufacturers are now the ones pushing the technology envelope. This paper discusses current trends within modern nonlinear measurement systems to determine who is leading whom and whether the aforementioned paradigm is shifting.

A new practical reconfigurable output network for a multiband reconfigurable power amplifier (PA) is proposed for universal mobile telecommunications system (UMTS) handset applications. The proposed reconfigurable network can reconfigure the output power and the output path, as well as the frequency. It consists of a power-reconfigurable network, a frequency-reconfigurable network, and a path-selection network. In this paper, its reconfiguration principle is described to extract key design parameters for the reconfigurable PA implementation. To demonstrate the performance of the proposed structure, a 5 mm × 6 mm multiband reconfigurable PA module is developed for UMTS high- and low-frequency band application. The fabricated PA module can cover any three bands out of five popular high- and low-frequency UMTS bands. To enhance the efficiency during low output power operation, the authors' stage-bypass technique is also employed. The fabricated PA module showed adjacent channel leakage ratios better than -39 dBc up to the rated linear output power and power-added efficiencies of higher than 39% at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> =28 dBm over all the UMTS frequency bands. Efficiency degradation was limited to less than 2% compared to the single-band PA. Measured RF performance of the reconfigurable PA validates the usefulness of the proposed reconfigurable structure for multiband UMTS applications.

This thesis researches the design of transceiver front-end RF amplifiers for Bluetooth applications in GPDK 45 nm CMOS technology. The target of the design was to minimize the transceiver's power consumption while achieving the best device operating performances. The design of a band-pass low noise amplifier (LNA) used for the receiver and the design of a power amplifier (PA) used for the transmitter were presented. Both amplifiers were designed in 45 nm CMOS technology with a DC supply voltage under 1.2 V to meet Bluetooth specifications at 2.45 GHz operating frequency. The LNA was designed to achieve a minimum small signal gain of at least 15 dB10 with a NF less than 2 dB10 and a reasonable input range for linearity at 1 mW operating power consumption. The PA was designed based on class E switching power amplifier configuration to achieve a minimum of 40% drain efficiency for 100 mW (Bluetooth Class 1) output power. Research on low power high performance Bluetooth device front-end RF amplifiers was conducted through studies of wireless communication modulation schemes, impedance matching networks, and trade-offs between performance parameters. In summation, this thesis searched for, explored, and analyzed possible methodologies that could be used to design RF CMOS amplifiers of Bluetooth applications.

We present in this work a reconfigurable broadband highly-efficient medium-power power amplifier (PA) design in 22nm FD-SOI for potential millimeter-wave (mm-Wave) 5G (5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> Generation) applications. The broadband PA is targeted to cover the key part of the 5G FR2 band (i.e., 24.25 to 43.5 GHz), with P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> ~16 dBm and high power-added-efficiency (PAE) and excellent linearity. The post-layout parasitic extracted (R+C+CC) simulations performed in Calibre suggest this PA reaches max. PAE > 35% around 20 GHz, while still maintaining higher than 16% max. PAE across the entire 20 GHz - 50 GHz band. Using an LTE 64-QAM modulated 250 MHz input at 28 GHz, this design boasts an impressive simulated linearity performance with ACLR <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-</sup> /ACLR <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1+</sup> = -36.6/-36.2 dBc at P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> = 11.4 dBm. With the broadband, high PAE and linearity performance, this reconfigurable CMOS PA appears attractive for potential mmWave 5G applications.

Preface. About the Authors. Acknowledgments. 1 Power Amplifier Fundamentals. 1.1 Introduction. 1.2 Definition of Power Amplifier Parameters. 1.3 Distortion Parameters. 1.4 Power Match Condition. 1.5 Class of Operation. 1.6 Overview of Semiconductors for PAs. 1.7 Devices for PA. 1.8 Appendix: Demonstration of Useful Relationships. 1.9 References. 2 Power Amplifier Design. 2.1 Introduction. 2.2 Design Flow. 2.3 Simplified Approaches. 2.4 The Tuned Load Amplifier. 2.5 Sample Design of a Tuned Load PA. 2.6 References. 3 Nonlinear Analysis for Power Amplifiers. 3.1 Introduction. 3.2 Linear vs. Nonlinear Circuits. 3.3 Time Domain Integration. 3.4 Example. 3.5 Solution by Series Expansion. 3.6 The Volterra Series. 3.7 The Fourier Series. 3.8 The Harmonic Balance. 3.9 Envelope Analysis. 3.10 Spectral Balance. 3.11 Large Signal Stability Issue. 3.12 References. 4 Load Pull. 4.1 Introduction. 4.2 Passive Source/Load Pull Measurement Systems. 4.3 Active Source/Load Pull Measurement Systems. 4.4 Measurement Test-sets. 4.5 Advanced Load Pull Measurements. 4.6 Source/Load Pull Characterization. 4.7 Determination of Optimum Load Condition. 4.8 Appendix: Construction of Simplified Load Pull Contours through Linear Simulations. 4.9 References. 5 High Efficiency PA Design Theory. 5.1 Introduction. 5.2 Power Balance in a PA. 5.3 Ideal Approaches. 5.4 High Frequency Harmonic Tuning Approaches. 5.5 High Frequency Third Harmonic Tuned (Class F). 5.6 High Frequency Second Harmonic Tuned. 5.7 High Frequency Second and Third Harmonic Tuned. 5.8 Design by Harmonic Tuning. 5.9 Final Remarks. 5.10 References. 6 Switched Amplifiers. 6.1 Introduction. 6.2 The Ideal Class E Amplifier. 6.3 Class E Behavioural Analysis. 6.4 Low Frequency Class E Amplifier Design. 6.5 Class E Amplifier Design with 50# Duty-cycle. 6.6 Examples of High Frequency Class E Amplifiers. 6.7 Class E vs. Harmonic Tuned. 6.8 Class E Final Remarks. 6.9 Appendix: Demonstration of Useful Relationships. 6.10 References. 7 High Frequency Class F Power Amplifiers. 7.1 Introduction. 7.2 Class F Description Based on Voltage Wave-shaping. 7.3 High Frequency Class F Amplifiers. 7.4 Bias Level Selection. 7.5 Class F Output Matching Network Design. 7.6 Class F Design Examples. 7.7 References. 8 High Frequency Harmonic Tuned Power Amplifiers. 8.1 Introduction. 8.2 Theory of Harmonic Tuned PA Design. 8.3 Input Device Nonlinear Phenomena: Theoretical Analysis. 8.4 Input Device Nonlinear Phenomena: Experimental Results. 8.5 Output Device Nonlinear Phenomena. 8.6 Design of a Second HT Power Amplifier. 8.7 Design of a Second and Third HT Power Amplifier. 8.8 Example of 2nd HT GaN PA. 8.9 Final Remarks. 8.10 References. 9 High Linearity in Efficient Power Amplifiers. 9.1 Introduction. 9.2 Systems Classification. 9.3 Linearity Issue. 9.4 Bias Point Influence on IMD. 9.5 Harmonic Loading Effects on IMD. 9.6 Appendix: Volterra Analysis Example. 9.7 References. 10 Power Combining. 10.1 Introduction. 10.2 Device Scaling Properties. 10.3 Power Budget. 10.4 Power Combiner Classification. 10.5 The T-junction Power Divider. 10.6 Wilkinson Combiner. 10.7 The Quadrature (90 ) Hybrid. 10.8 The 180 Hybrid (Ring Coupler or Rat-race). 10.9 Bus-bar Combiner. 10.10 Other Planar Combiners. 10.11 Corporate Combiners. 10.12 Resonating Planar Combiners. 10.13 Graceful Degradation. 10.14 Matching Properties of Combined PAs. 10.15 Unbalance Issue in Hybrid Combiners. 10.16 Appendix: Basic Properties of Three-port Networks. 10.17 References. 11 The Doherty Power Amplifier. 11.1 Introduction. 11.2 Doherty's Idea. 11.3 The Classical Doherty Configuration. 11.4 The 'AB-C' Doherty Amplifier Analysis. 11.5 Power Splitter Sizing. 11.6 Evaluation of the Gain in a Doherty Amplifier. 11.7 Design Example. 11.8 Advanced Solutions. 11.9 References. Index.

We discuss the broadband design of high-efficiency GaN power amplifiers (PAs) using continuous modes. A Machine Learning approach to the full EM-based optimization of a hybrid design is first outlined and demonstrated experimentally. We then consider the challenges of achieving high efficiency in a broadband integrated PA, including the features of GaN transistors that facilitate broadband operation. It is shown that proper sizing of transistor can lead to an optimum load resistance close to 50fl, thereby extending the bandwidth of the output matching network of the PA in an integrated environment. We present techniques to realize the continuous-mode operation in an integrated GaN PA, with low loss and compact chip size. Finally, we show predicted results for the integrated GaN PA implementation.

In this paper, we present a design of a concurrent dual-band power amplifier operating at 5.8 GHz and 9.4 GHz employing a MMIC technology for wireless communications. The active device used is a 0.25 µm AlGaN/GaN HEMT from WIN Semiconductor, Taiwan. The design goal is to achieve the high-efficiency while still retaining other important metrics including output power and power Gain at concurrent dual frequency bands. The performance of the designed amplifier is evaluated at both small and large signal levels through theoretical analyses and simulation using a Keysight ADS simulator. The developed dual-band amplifier delivered a 47% PAE with 30.5 dBm output power and 12.5 Gain at 5.8 GHz, and a 37% PAE with 30.2 dBm output power and 12.2 Gain at 9.4 GHz.

WLAN is a widely used standard telecommunication protocol. Currently IEEE802.11ac standard has some limitations along with the increasing need for fast communication and able to serve many devices. The development of the IEEE 802.11ax standard is expected to overcome these limitations. Some challenges on the design of power amplifiers also appear as the development of 802.11ax standard. Power amplifiers on the access point are expected to provide a minimum output of 30dBm. This paper explains the design and modeling of power amplifiers on access point using load pull method. Based on the design and test result using CGH27030 transistor with simulation approach harmonic balance obtained that the output power of half wave obtained optimum value 33,023 dBm at input value 19 dBm and EVM equal to 4,8%.

This paper presents a method for bandwidth extension in high-efficiency power amplifier (PA) design. With a phase shift in voltage waveform of the continuous class-F mode, real part of harmonic impedance is generated to expand the impedance design space at the expense of little lossy of performance. The simulation and measurement, conducted on a broadband PA covering 1.9-3.1 GHz based on the proposed method, show a good agreement with the theory. Measured results show that the fabricated PA has a drain efficiency of 66.5%-75% when delivering 41-42.3 dBm output power with a gain of 11-12.7 dB. Under a 20-MHz LTE signal excitation at 2.6 GHz, the PA exhibits an adjacent channel leakage ratio of -36.5 dBc at an average output power of 35 dBm without linearization.

RF power amplifiers are one of challenging blocks in designing radio frequency transceivers, this is due to non-linearity behavior of power amplifiers that leads to inter-modulation distortion. This paper presents the design of wide-band power amplifier which combined with parallel coupled line band pass filter at the input and output of power amplifier to allow the only required frequency band to pass through the power amplifier. Class-A topology and ATF-511P8 transistor are used in this design. Advanced Design System software used as a simulation tool to simulate the designed wide-band power amplifier. The simulation results showed an input return loss (S11) which less than -10dB, and gain (S21) is higher than 10 dB over the entire frequency band and considers as flat as well. The designed amplifier is stable over the bandwidth (K&amp;gt;1). Inter-modulation distortion is -56.919dBc which is less than -50dBc with 10dBm input power. The designed amplifier can be used for the microwave applications which include weather radar, satellite communication, wireless networking, mobile, and TV.

Reconfigurable multi-mode multi-band power amplifier, due to its unique architecture and numerous applications, has been of great interest to both academic society and micro-wave/RF industry, especially with the rapid evolution of wireless communications. Although many attempts have been made, it still remains as a very difficult challenge to the development of the RF/microwave technologies. In this paper, an overview is provided to review the new advances in reconfigurable multi-mode multi-band power amplifiers, in terms of both new architecture and design methodology. The recent development status and trends are also presented. A few examples, represented by a series of MMMB products, are also given, which unambiguously indicates that with reconfigurable technology, the power amplifier can have wider bandwidth, better performance and lower cost. This also makes reconfigurable architecture a promising technology for future multi-mode multi-band power amplifier design.

This paper presents a step by step design of power amplifiers at 2.4 GHz (for WLAN applications) and on-chip linearization of these amplifiers. CMOS power amplifiers are designed at 2.4 GHz with output power ranging from 30 mW to 100 mW with efficiency varying from 20%-40%. Two or three stages are cascaded according to the gain and efficiency requirements. The topology used for 2.4 GHz amplifier is also verified as a part of an FM transmitter at 900 MHz. All these integrated power amplifiers are not intended to have a very good linearity. At the later part of this work, feedforward technique is used for linearization of a 2.4 GHz two-stage power amplifier in 0.25 /spl mu/m CMOS8 process. The power output of the linear amplifier (in push-pull configuration) is 17 dBm with 20% efficiency. The in-band non-linearity (from two-tone simulations) is given by 3/sup rd/ order inter-modulation product and is about 40 dBc. For on-chip combining, transformers and baluns are used. All the circuits are simulated using CADENCE tools (ICFB). Inductors, transformers and baluns are designed and simulated using ASITIC tools. The power amplifiers are currently under fabrication in CMOS8 (0.25 /spl mu/m) and CMOS9 (0.18 /spl mu/m) processes.

This paper presents the design of a multi-octave power amplifier (PA) using extended class B to class J continuous mode. In a multi-octave PA, an overlapping exists between the higher harmonic frequencies of the lower octave and the fundamental frequency of the higher octave. Therefore, a PA mode with overlapping between fundamental and second harmonic impedances is suitable to design a multioctave PA. An extended class B to class J continuous mode consists of overlapping between fundamental and second harmonic impedances. However, the design of a multi-octave PA is not straightforward. The impedance selected in each octave is important to design a highly-efficiency multi-octave PA. Therefore, this paper presents a methodology to choose the appropriate load in each octave to design extended class B to class J continuous mode PA. This paper also presents a valid range of design variables for the transistor&#x2019;s reliable operation. The proof of concept PA has been designed using 10 W Wolfspeed GaN HEMT CGH40010F. The designed PA operates from 0.75 to 2.75 GHz. The corresponding fractional bandwidth is 114.2&#x0025;. The measured drain efficiency, power added efficiency, and output power are 60-73.6&#x0025;, 53-67.8&#x0025;, and 39.3-42.3 dBm, respectively. The measured carrier to third-order intermodulation distortion is better than -15 dBc when tested with a 20 MHz spacing two-tone signal.

In this letter, a new Bayesian optimization (BO) method with dynamic feasible region shrinkage (DFRS) technique for power amplifier (PA) design is proposed. As a powerful optimization tool, it provides a more effective way to optimize the performance of PA than the embedded commercial optimization tools. It also has a better convergence speed than the existing fixed mode acquisition function. Results show that the new technique provides a great optimization for PA design, not only for circuit optimization but also for electromagnetic (EM) optimization.