Reliability Analysis of System-in-Package Module Based on Physics of Failure

Review of shelf life evaluation methods and a physics of failure approach for shelf life estimation for electronic components

Demand for higher levels of integration with cost effective solution have driven the increased use of and innovation in System in Package module for Radio Frequency (RF) new products. System in Package (SiP) module high integration capability allows for wide range of power and frequency applications ranging from low power remote heads to massive Multiple-Input Multiple-Output (MIMO) systems. System in Package module employs both active devices and passive components, such as inductor, capacitor and resistor, together with other materials like substrate, solder and gold wire. This paper discusses the characterization study of solder extrusion during the development work for a new product employing new substrate plating. The study covered two characterization activities on key factors affecting solder extrusion under inductors namely, material characterization and process characterization. Materials characterization covered the study of new substrate plating and the inductor type considered under the new product which may impact solder extrusion. Process Characterization covered the study of solder paste screen print process versus their solder extrusion output response. Characterizations resulted to the definition of optimum pre-mould plasma cleaning parameter and solder screen printing process parameters for the new product, the results of which were integrated in its further development, qualification and production release.

The major concerns posed by system-in-package (SiP) designs for network applications are the interconnection reliability between the memory plastic ball grid array (PBGA) package and the SiP module, which we refer to as 2nd-level interconnection, and between the SiP module and the system board, which we refer to as 3rd-level interconnection, induced by thermomechanical stress to the large SiP module, i.e., 55 × 55 mm2 package body size. In this paper, finite element analysis (FEA) and design of experiment (DOE) case studies were used to evaluate the 2803-pin flip chip SiP (FCSiP) and to determine the best construction of the SiP module and optimize the assembly material set. Heat spreader (lid) thickness, heat spreader material, and under-fill implementation were considered in the stress and fatigue lifetime FEA case studies and long-term solder joint reliability, which was accelerated thermal cycle (ATC) tested at operating temperatures from 0 to 100°C. Another important factor in the system-level reliability is an external heat sink, and its compressive force effect was also investigated in the ATC test. In addition, short-term mechanical reliability tests, such as the 4-point monotonic bend test based on the IPC-9702 specification and mechanical shock test based on the JESD22-B110A standard, were also evaluated for the 2803-pin FCSiP qualification. Finally, the results of these experiments were compared with the FEA data in a correlation process.

This paper presents design and implementation of a dual-band RF system-in-package (SiP) module for radar application. Four channel RF transceivers, each of which consists of dual-band RF front-end, ADC and DAC, are integrated in this SiP module. S and P band RF front-end of the transceiver employ common Intermediate Frequency (IF) window to share digitization circuits efficiently. To achieve more miniaturized package level of SiP, Package-on-Package technology is adopted and realized by stacking two multi-layer organic substrates vertically, which interconnected by Through Mold Via (TMV) and BGA. Dual-band RF front-end is mounted on the top RO4350B substrate, and four-channel ADC and DAC are molding on the bottom BT substrate. With the integration of 50 chips and 251 passive components, this SiP module retains small form factor and measures $\pmb{3.8\times 4\times 0.4}\mathbf{cm}^{\pmb{3}}$ . The simulation results show that the insertion loss of RF transmission paths are better than 0.4 dB with 60 dB channel isolation, the crosstalk between analog and digital paths is less than -60 dB, and each chip junction temperature is below 100°C in the condition of full load. The above evaluation indicates that the proposed RF SiP module can achieve the optimization of electrical performance, reliability and miniaturization simultaneously.

Combining with the practical engineering case, this paper decomposed and analyzed the process of electronic products’ reliability assessment based on the Physics of Failure (PoF) method. The first step is to build a digital prototype model and then a PoF model. The second step is to use the Monte Carlo sampling method to obtain the failure samples of different fault points based on the PoF model. The third step is forming the failure DFs by fitting the failure samples. The fourth step is using the failure DF to calculate the Time to Failure (TTF)of the components. Finally, the paper can obtain the time of the TTF and the failure DF by applying the competitive failure principle. Compared with the reliability evaluation method based on test data, the reliability evaluation method based on PoF is more economical and efficient.

According to Cisco’s Visual Networking Index Forecast [1], the amount of internet traffic will quadruple by 2015, driven by the increase of mobile devices and video content in the network. To meet such explosive demand, the industry has been developing new packaging solutions that will enable engineers to pack more functions and deliver higher speed with same or smaller form factors. An innovative System-in-Package (SiP) module has been developed as cost-effective packaging technology. This ultra large 90x90 mm module accommodates fourteen DDR3 memories and one flip chip ASIC with an organic substrate. The challenges and corresponding solutions in packaging design, process, and assembly of such a large organic BGA module has been outlined by Ahmad, et al. [2]. In this study, a full scale reliability evaluation of the SiP module assembly has been conducted. The evaluation included 0/100˚C Accelerated Temperature Cycling (ATC), mechanical shock under different impulse G levels, and mechanical four-point bend. The test vehicle of this study has been designed to include multiple chains for real time continuity monitoring of interconnects at different levels, i.e. from ASIC flip chip to module substrate, from DDR3 memory components to module substrate, and from SiP module to Print Circuit Board (PCB). Some of those daisy chains were dedicated to the interconnects in high stress regions such as die shadow areas and package corners to allow pinpointing of the failures at the exact locations during the reliability evaluation. Strain gauges were attached onto the PCB during shock and bend testing so that the board level strains at failure could be recorded. Furthermore, an acoustic emission system has also been adopted during 4-point bend testing to study the onset of pad cratering. Finite element analysis has also been performed to evaluate the stress and strain distributions of the solder joint interconnect structure during shock and bend testing. The insightful results of this study are valuable to design robust and reliable ultra large BGA module assemblies.

A combined physics of failure and Bayesian network reliability analysis method for complex electronic systems

The system-in-package (SiP) is widely used in communication device that integrated multi components and packages into one system. However, the board level reliability performance becomes more important, especially cyclic bending test. In the work, both experimental and numerical model are performed to investigate the four point cyclic bending test with different load displacement. The bending test experiment was analyzed by Weibull method to calculate the solder fatigue life of SiP module. A three-dimension finite element method (FEM) and the Anand's visco-plasticity Model are used to simulate solder's creep behavior under cyclic bending test. It was constructed and experimentally benchmarked to qualitatively figure out solder joint failure location in whole package and crack position in solder interconnection. Besides, the constructive index, plastic work density (PWD) accumulated per cycle, is used to evaluate the risk of solder fatigue cracking failure and be correlated well from experimental characteristic cycles. This work provides design guideline for SiP module board level reliability under bending test. The factors that underfill dispensing effect and material type suggestion are also considered in this work.

The automotive market for the IC (integrated circuit) packaging industry has grown significantly over the last 8 to 10 years due to its increasing need for automation, higher performance, and the more stringent reliability requirements in the vehicles. These changes in the automotive market will enable cars to be more reliable and intelligent at a reasonable cost. To address the increasingly complex demands of the automotive market, the semiconductor packaging industry is shifting its focus to prioritize the development of advanced and more reliable packages for next generation automotive market requirements. Automotive IC’s have traditionally been assembled in mature wirebond type packages. Due to the increasing complexity and higher performance requirements of automotive applications, the packaging industry is moving towards very high performance flip chip, fan out wafer level and very recently system in package (SiP) solutions for automotive ADAS, infotainment, GPS, camera, radar, driverless car and many more applications. SiP packages or modules are getting more momentum for complex functionality for high computing automotive such as L3 or L4 automotive. In this study a comprehensive view of the changing packaging landscape from standard flip chip interconnect to highly complex SiP or module packages and the corresponding reliability grade level requirements (G2, G1) will be discussed. Special design, process and BOM (bill of materials) are the most important parameters to consider for high reliability, complex SiPs for automotive applications. In this study, detailed design parameters, step-by-step package development, along with the optimal BOM are evaluated. Both package and board level data were analyzed to qualify automotive SiP for G2 and G1 conditions. Relative packaging cost vs performance for traditional packages to advanced SiPs are evaluated in the study.

For getting more economy and smaller electronic products, technology of system in package (SiP) could complement the technology of system on a chip (SoC) perfectly. About SiP technology, we chose integral substrate technology to realize embedded passives, and used fine process such as high density interconnection (HDI) technology with a special dielectric material to achieve specific circuit functions. The special material is a high dielectric constant (Hi-DK; DK>40 @ 1GHz) material, which is suitable for Multi-Layer Printed Wiring Board (PWB) lamination process, and it was used to fulfill embedded capacitors. In the past years, we had utilized the technology to design Bluetooth/sup TM/ module, or other RF circuits. Furthermore, this technology is more economy than any other SiP processes, like Low Temperature Co-fired Ceramic (LTCC) substrate or silicon substrate, because it bases on the conventional PCB process. In this paper, we introduce not only the embedded capacitors but also some functional embedded passives in RF front-end circuits design on the Hi-DK organic substrate. Moreover, the RF front-end circuits include some functional passive elements: band pass filter, balun, and antenna, etc. Thus, in high frequency circuits, this kind organic substrate can reduce the module size, and in high-speed digital circuits, it also provides inexpensive decoupling capacitors. In the future, we will use this cost-effective technology to design analog and digital circuits on the same board, and the technology of SiP and SoC can be co-designed.

A fully integrated system-in-package (SiP) for UHF (860-960MHz) RFID mobile reader is presented. The SiP is made up of an UHF transceiver, a power amplifier (PA), and two baluns. The UHF transceiver was designed in TSMC 0.18µm Si CMOS and the PA was developed with InGaP/GaAs hetero-junction-bipolar transistor (HBT) technology. The transceiver IC is fully integrated for mobile UHF RFID applications and the PA has high efficiency and linearity with 24dBm output power for wireless RFID communications over a distance of 1m. The total size of the SiP module is 11mm × 11mm. The measured data show a transmitter gain of 19.2dB, total current of 253mA and adjacent channel power ratio (ACPR) of -41.8dBc with the second harmonic performance of -57.6dBc. Also, TX-RX leakage was reduced by careful power amplifier and board designs in small SIP module implementation.

Recently the requirement for portable products, such as mobile phones, digital cameras, PDAs and game consoles, has been increasing rapidly and consumers want to easy to carry them and have multi-functions as well as lower price. So it's necessary to develop the semiconductor packages with thin and small size, high performance and low cost. And various types of SiP (system in package) technologies have been developed to satisfy these requests. The embedded packages are one or more chips are embedded at the inside of the substrate and one of the technologies to realize the packages with thin and small size and high performance but there is much room for improvement, such as reliability issues, yields, etc. Therefore, wafer level embedded SiP (WL-ESiP) which daughter chip is embedded on mother chip by mold compound without substrate has been developed. In this study, to confirm our wafer level embedded SiP structure and processes, feasibility test has been performed by fabrication of molded dies with 2 stacked dies at wafer level and verified by reliability tests of MSL2a, PCT (121?C/100%RH/2 atm), HTS (150?C) and TC (-65/150?C) for molded dies. To realize this embedded SiP, redistribution, solder and Cu bumping, flip-chip bonding, molding, Si and mold thinning and ball mounting technologies have been developed and applied at the wafer level. After feasibility test, to confirm the effect of the package size and material for the WL-ESiP, the reliability tests of MSL2a, PCT (121?C /100%RH/2 atm), TC (-40/125?C) and HTS (150?C) have been performed for molded dies with die sizes of 4 mm ? 4 mm and 6 mm ? 6 mm, 3 types of dielectric materials and 3 types of mold materials and the test vehicle with MC3 mold, D2 dielectric and 4 mm ? 4 mm size passed MSL2a, 168 hrs of PCT, 2000 cycles of TC and 1000 hrs of HTS. Also, the stress simulation of mold dies has been performed and the location with maximum stress has been confirmed. As a result of reliability tests and stress simulation for the molded die, WL ESiP test vehicle with daisy chain has been designed and fabricated to evaluate the package level and board level reliabilities. The size of mother and daughter chips is 4 mm ? 4 mm and 2.95 mm ? 2.31 mm respectively and daughter chip has 70 um thickness. For the fabricated WL-ESiP, package level reliability tests of MSL2a, PCT (121?C /100%RH/2 atm), TC (-40/125?C) and HTS (150?C) has been performed. And TC (-40/125?C) and drop (1500 G/0.5 ms) tests will be also performed at board level.

Solder fatigue failure is one of the primary wear out failure mechanisms limiting reliability in microelectronics flip chip packaging. Solder fatigue failure occurs when a crack initiates and subsequently propagates through the entirety of the solder joint causing an electrical open. Crack initiation and propagation within a solder joint is caused by a cyclic application of stress, typically induced by exposure to temperature cycle excursions. Understanding the relationship between thermal cycling during product use and the accelerated thermal cycles used for testing is critical for predicting device reliability. MIL-PRF-38535 is the guiding aerospace and high reliability General Specification for Integrated Circuits (Microcircuits) Manufacturing that defines manufacturing, qualification and certification requirements for products to be listed on the Defense Logistic Agency’s (DLA) Qualified Manufacturer Listing (QML). Revision M of this standard, targeted for release in 2022, for the first time includes the use of lead-free solder alloys and organic substrates in the manufacturing of QML flip chip products. Hence there is a strong need to understand the physics-of-failure (PoF) concerning solder fatigue of lead-free flip chip assemblies. This paper demonstrates how finite element modeling can be used to predict solder fatigue for flip chip package assemblies. The authors have leveraged fatigue lives measured for different flip chip daisy chain package configurations, as well as fatigue lives defined and available in published papers. The authors then use the resulting lead-free solder fatigue model to perform parametric studies looking at the impact of different die sizes, underfill material properties, and package substrate materials. Comparisons are also made between eutectic Sn/Pb and lead-free fatigue life predictions. In addition, the authors demonstrate how solder fatigue predictions can be de-rated to use conditions in order to make reliability assessments for flip chip package assemblies. This ultimately leads to a better understanding of the impact of solder alloy and material selection on the mission life of aerospace and high reliability products that fall under the changes introduced in MIL-PRF-38535 Revision M.

Since the physical structure and mathematical models are more complex, reliability analysis in practical engineering can be expensive and difficult. A two-level multifidelity metamodel method for reliability analysis is introduced. Following the surrogate model in most of the relevant works, low-fidelity data and high-fidelity data are integrated by co-Kriging model. Besides, the co-Kriging model also provide an approximation for initial performance function. Bayesian method is adopted in model solution and a hybrid Markov chain Monte Carlo (MCMC) sampling algorithm is proposed. High-fidelity response of reliability performance function is estimated by the conditional distribution derivation based on Bayesian theory. Failure domain is identified by indicator function in sampling space that consists of samples derived from MCMC. Accordingly, failure probability estimations are obtained using Monte Carlo simulation (MCS). It is demonstrated through an illustrative example that the proposed method is valid and accurate.

In current wireless applications, plastic packaging technologies are widely used for the components such as power amplifiers and SIP (system in package) modules. The semiconductor devices in those components dissipate significant amount of heat and requires effective thermal management to ensure the device reliability. The devices (semiconductor dies) in these packages are usually assembled by wire-bond interconnections on PCB substrates and encapsulated with epoxy mold compound (EMC) by a transfer molding process. There are two major paths for thermal dissipations in these plastic packages: a. through the front side of the die and b. through the backside of the die. For low cost plastic packages using conventional molding process, more than 90% of the heat dissipation is through the backside of the die. It is extremely important that the heat path of the system is well designed and optimized. In this paper, technologies for thermal management in this type of packages are discussed. Critical design rules are presented and practical solutions are proposed