Resistorless switched-capacitor current reference based on the MOSFET ZTC condition

Electromagnetic Interference (EMI) disturbances coupled in the power supply of voltage and current references can severely degrade their performance, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant NMOS-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm2 of silicon area while consuming just 1.15 μW. Post-layout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/°C, for the temperature range from −55 to 125 °C. An EMI source of 4 dBm (1 V pp ) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum dc shift and Peak-to-peak ripple of −0.17 % and 822 μV pp , respectively.

Ruthenium dioxide (RuO2) is a stable conductive and semi-transparent oxide. It has been investigated in the past for several applications: (i) good diffusion barrier properties in integrated circuit processing [1], (ii) improvement of reliability when used as electrodes for ferroelectric capacitors [2], and (iii) thin film resistors capable of achieving zero temperature coefficient [3, 4]. The property of nearly zero temperature coefficient of resistance is very important in circuits requiring a high degree of accuracy. Previously there are several reports on the characteristics of the microstructure and resistivity of sputtered RuO2 under different deposition conditions such as oxygen flow rate and annealing temperature [3–6]. But there are still uncertainties concerning the physical mechanisms responsible for the zero temperature coefficient, and the type of charge carriers. In this letter, we will provide a more comprehensive description of the electrical characteristics of reactively sputtered RuO2 film, including some Hall effect measurements which have not been reported before. N-type silicon wafers with (100) orientation were chosen as the substrates. Silicon dioxide (SiO2) was grown by thermal oxidation to a thickness of 500 nm. RuO2 thin films were reactively sputtered by r.f. magnetron sputtering of a ruthenium target in a mixture of Ar and O2. The relative partial pressure of oxygen to the total gas pressure, p(O2)/p(O2 + Ar), was set to be 45%. Prior to sputtering, the system was pumped down to a base pressure of less than 3 × 10−7 Torr. During sputtering, the input power was about 5 W/cm2, and the total pressure was 0.6 Pa. The substrate temperature during deposition was varied between 50 ◦C and 150 ◦C. The samples were then annealed in a nitrogen ambient at different temperatures from 200 to 500 ◦C for 30 min. Rutherford backscattering (RBS) verified that the atomic ratio of oxygen to ruthenium atoms in the deposited films is 2. The microstructures of the films prepared under different conditions were examined by X-ray diffraction (XRD). The resistivity of the films were measured in Van der Paul structure on a die size of 1 cm2 for temperatures ranging from 30 K to 400 K. Hall measurements on the films were also performed at 30 K with the same sample structure. The temperature dependence of the resistivity of the RuO2 films deposited at 100 ◦C substrate temperature and annealed at different temperatures is shown in Fig. 1. The behavior for samples deposited at other substrate temperatures 50 ◦C and 150 ◦C are similar (not shown). In Fig. 1 the resistance values at the low temperatures around 30 K are almost independent of temperature for all annealing conditions. But at temperatures above 100 K, the resistance shows definite trends with temperature variation. The temperature coefficient is negative for annealing temperatures of 200 ◦C and 300 ◦C, but is positive for annealing temperatures of 400 ◦C and 500 ◦C. To correlate with the microstructure, the X-ray diffraction patterns (XRD) are shown in Fig. 2 for the same sample. It shows that the film is crystallized with a sharp peak at 28 ◦ (corresponding to

A curvature-compensated CMOS voltage reference using [formula omitted] characteristics

Tradeoff between the transistor reconfigurable technology and the zero-temperature-coefficient (ZTC) bias point on BESOI MOSFET

Organic field-effect transistors (OFETs) have broad prospects in biomedical, sensor, and aerospace applications. However, obtaining temperature-immune OFETs is difficult because the electrical properties of organic semiconductors (OSCs) are temperature-sensitive. The zero-temperature coefficient (ZTC) point behavior can be used to achieve a temperature-immune output current; however, it is difficult to achieve in organic devices with thermal activation characteristics, according to the existing ZTC point theory. Here, the Fermi pinning in OSCs is eliminated using the defect passivation strategy, making the Fermi level closer to the tail state at low temperatures; thus threshold voltage (VT) is negatively correlated with temperature. ZTC point behaviors in OFETs are achieved by compensation between VT and mobility at different temperatures to improve its temperature immunity. A temperature-immune output current can be realized in a variable-temperature bias voltage test over 50000s by biasing the device at the ZTC point. This study provides an effective solution for temperature-immune OFETs and inspiration for their practical application.

A novel current reference with low temperature and supply sensitivity and without any external component has been developed in a 0.25 /spl mu/m mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit similar to a beta multiplier. An NMOS transistor in triode region has been used in place of a resistor in conventional beta multiplier to achieve a current which has a negative temperature coefficient and only oxide thickness dependent. The BGR voltage has a positive temperature coefficient to cancel the negative temperature coefficient of the beta multiplier. The simulation results using Bsim3v3 model show max-to-min fluctuation of less than 1% over a temperature range of -20/spl deg/C to +100/spl deg/C and a supply voltage range of 1.4 V to 3 V with /spl plusmn/30% tolerance for all of the used on- chip resistors. The maximum current variation is slightly less than the oxide thickness variation in the process corners.

ABSTRACTThis paper proposes a nanowatt voltage reference (VR) with temperature coefficient compensation. All transistors work in the subthreshold region. The complementary‐to‐absolute‐temperature (CTAT) voltage and proportional‐to‐absolute‐temperature (PTAT) voltage are mainly generated by two NMOS transistors with different threshold voltages. At the same time, a simple temperature compensation circuit is designed to optimize the temperature coefficient at high temperatures, so that the proposed VR circuit can generate a reference voltage with a wider temperature range and a lower temperature coefficient. The proposed VR circuit is implemented using a standard 0.18‐μm CMOS process with an active area of only 0.022 mm2. The postlayout simulation results show that the proposed VR circuit generates a reference voltage of 308.21 mV at room temperature. Its temperature coefficient is 6.4 ppm/°C over a temperature range of −40°C°C–140°C, with a power consumption of 7.4 nW. The voltage line sensitivity (LS) is 0.098%/V, and the power supply ripple rejection (PSRR) is −72 dB @DC and −42 dB @10 MHz.

This work investigates the possibility to tune the zero-temperature-coefficient (ZTC) points in partially depleted (PD) SOI nMOSFET technology by controlling the body-source forward bias (VBS). Measured transconductance and drain current in the saturation region at temperatures between 25 and 200degC were observed for various body-source forward bias conditions. It is found that the variation of threshold voltage (VTH) with body bias has an influence on ZTC points. The measurement results show wide voltage-range of gate-voltage giving either the transconductance ZTC point (VGS,ZTC9m) or the drain-current ZTC point (VGS,ZTC1DS) opening important opportunities in RF circuits design for nigh temperature applications.

This paper reports the temperature influence on the Back Enhanced (BE) SOI MOSFET fabricated with two different source/drain contact electrodes: Ohmic and Schottky. The BE SOI MOSFET (Patent BR 102015020974-6, 2015) is a kind of undoped junction-less SOI transistor, which works like an n-type or p-type MOS, depending on the back bias conditions. In spite of the Schottky contact at source/drain is mandatory in order to have both type of transistor working in a similar way, the use of Ohmic contact may present some specials advantages. The results showed the presence of a ZTC (Zero Temperature Coefficient) bias condition only in the device with Ohmic source/drain contact. It was observed that the Schottky contact resistance decreased when the temperature increases resulting in a higher current and consequently the absence of the ZTC. This effect is explained through experimental measurements and simulation.

Two theories of breakdown mechanism in silicon junction diodes have at present been advanced, avalanche and field emission, one by Zener and the other by Von Hippel and Frohlich. At various times physicists have supported one or the other of these theories operating independently, but the development of the low-voltage silicon reference diode has indicated that the two methods of breakdown can occur simultaneously. An explanation of the peculiar behaviour of the voltage/temperature coefficient of such diodes can be made by incorporating both breakdown mechanisms. It is shown that very-close-tolerance devices must be used in experimental work. Comparison of the breakdown theories with experimental results shows that the breakdown of diodes at voltages less than 4.5 volts is due to field emission, greater than 6.5 volts is due to avalanche effects, and between 4.5 and 6.5 volts is due to a combination of both effects. Confirmation of these results is made by noise measurements. A characteristic surface of temperature coefficient of breakdown voltage shows skew properties which suggests that a diode having zero temperature coefficient over a wide range cannot exist for the currents and voltages considered.

This work presents a simulation study of the influence of temperature on the performance of dual material gate (DMG) vertical super-thin body (VSTB) FET. The introduction of DMG causes a drop in the off-state current (Ioff) by ~99.18% and DIBL by 20%. Drop in the Ioff enhances the on-to-off current ratio (Ion/Ioff) by ~98.85%. A rigorous investigation on temperature dependency of DC, analog/RF, and linearity metrics was carried out. The zero temperature coefficient (ZTC) bias point for the DMG device was observed to be nearly at a gate bias of VG = 0.41 V. Various DC figures of merit (FoM) such as subthreshold swing (SS), Ion/Ioff, and threshold voltage (VT) show improvement with temperature fall. Lowering in temperature also leads to enhanced analog/RF performance by offering superior gm, gd, Cgg, Cgd, maximum fT, maximum GBP, intrinsic delay, TGF, TFP, GFP, and GTFP. However, linearity metrics like gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point show better performance with an increase in temperature.

In this paper, a MOSFET-only voltage reference with novel curvature-compensation is proposed. In order to reduce the temperature coefficient in the proposed voltage reference, two proportional to absolute temperature voltages with opposite second-order order TC are added on a threshold voltage, which is achieved by a resistorless threshold voltage extractor. Besides, self-biased current source with feedback is realized at the same time, which can provide bias current for the whole voltage reference and enhance the performance of generated voltage reference without additional power consumption. Verification results of the proposed voltage reference implemented with 0.35µm technology process show that the temperature coefficient is 2.4 ppm/□ with a temperature range of −20□ to 80□ is obtained, and a 62.9 dB power supply rejection ratio is achieved with a 68nA maximum supply current.

Compensation of temperature effects in force-balanced microelectromechanical system accelerometers

A subthreshold nano‐power voltage and current reference with high‐order temperature compensation is proposed by taking advantage of the channel length modulation of MOS devices. Curvature compensation is implemented by providing proper compensating drain‐source voltages for the core devices of a first‐order CMOS reference such that the output nonlinear temperature factors can be compensated over a wide temperature range. In‐depth mathematical analysis is carried out to model the temperature dependency of the reference signals before and after compensation. As part of the analysis, Taylor expansion of the threshold voltage of MOS devices has been evaluated in a generalized fashion, enabling to clarify the complicated relationship between the high‐order temperature‐related terms of the output and design parameters. Simulated in a standard 0.18‐μm CMOS process, the minimum supply voltage of a proof‐of‐concept design is 1.0 V, providing 345 mV voltage reference with minimum temperature coefficient (TC) of 2.0 ppm/°C across the range of –40–140°C. The active area is 0.45 mm2 with around 200 nA current consumption. The DC line regulation is 0.23%/V, and the power supply rejection ratio (PSRR) is −63 dB at 10 Hz.

A novel design for temperature-compensated CMOS voltage reference sources by using the 1st order voltage reference taking into account the property of the conventional current generator is proposed to minimize the temperature coefficient because the 2nd order voltage reference obtained by the compensated nonlinearity of the base-emitters in complementary to absolute temperature has inherent complex problems due to the large scale circuits. A temperature coefficient of the proposed voltage reference source is estimated by using the current generator, which operates at smaller or larger temperature in comparison with the optimized operating temperature. The proposed temperature-compensated CMOS voltage reference sources are simulated by using a SMIC 0.35 gm CMOS technology. The temperature coefficient, obtained from the SMIC 0.35 μm CMOS technology, is 8.35 ppm/°C in a temperature range between ’40 and 125°C. The simulated results indicate that the proposed temperature-compensated CMOS voltage reference sources by using the 1 st order voltage reference taking into account the property of the conventional current generator can be used to decrease the temperature coefficient.