A curvature-compensated CMOS voltage reference using [formula omitted] characteristics

ABSTRACTThis paper proposes a nanowatt voltage reference (VR) with temperature coefficient compensation. All transistors work in the subthreshold region. The complementary‐to‐absolute‐temperature (CTAT) voltage and proportional‐to‐absolute‐temperature (PTAT) voltage are mainly generated by two NMOS transistors with different threshold voltages. At the same time, a simple temperature compensation circuit is designed to optimize the temperature coefficient at high temperatures, so that the proposed VR circuit can generate a reference voltage with a wider temperature range and a lower temperature coefficient. The proposed VR circuit is implemented using a standard 0.18‐μm CMOS process with an active area of only 0.022 mm2. The postlayout simulation results show that the proposed VR circuit generates a reference voltage of 308.21 mV at room temperature. Its temperature coefficient is 6.4 ppm/°C over a temperature range of −40°C°C–140°C, with a power consumption of 7.4 nW. The voltage line sensitivity (LS) is 0.098%/V, and the power supply ripple rejection (PSRR) is −72 dB @DC and −42 dB @10 MHz.

This paper presents a high-precision, low temperature coefficient (TC) CMOS bandgap reference for high-performance multi-channel ADC working under wide temperature range. A piecewise curvature compensation technique is proposed to extend its operating temperature range and keep its low temperature coefficient. A s-compensation technique is used to cancel the PTAT and non-PTAT spread of the output due to variation of β in the BJTs. Moreover, the trimming resistors are implemented to calibrate the 1st-order temperature coefficient and absolute value of the output voltage. The bandgap reference designed in 0.18μm CMOS process has a super low temperature coefficient of 2.1ppm/°C over a wide temperature of −55 ° C to 140 ° C, making it appropriate to provide reference voltage for a high-precision ADC.

A novel design for temperature-compensated CMOS voltage reference sources by using the 1st order voltage reference taking into account the property of the conventional current generator is proposed to minimize the temperature coefficient because the 2nd order voltage reference obtained by the compensated nonlinearity of the base-emitters in complementary to absolute temperature has inherent complex problems due to the large scale circuits. A temperature coefficient of the proposed voltage reference source is estimated by using the current generator, which operates at smaller or larger temperature in comparison with the optimized operating temperature. The proposed temperature-compensated CMOS voltage reference sources are simulated by using a SMIC 0.35 gm CMOS technology. The temperature coefficient, obtained from the SMIC 0.35 μm CMOS technology, is 8.35 ppm/°C in a temperature range between ’40 and 125°C. The simulated results indicate that the proposed temperature-compensated CMOS voltage reference sources by using the 1 st order voltage reference taking into account the property of the conventional current generator can be used to decrease the temperature coefficient.

The reference voltage is a core part of RFID tags, its performance directly determines the whole chip's life and performance. The temperature coefficient is one of the important performances of the reference voltage source and the high-order temperature compensation is an effective method to reduce the temperature coefficient of the reference source. A low temperature coefficient bandgap reference is designed based on the standard 65nm CMOS process, and the low-supply voltage operation with bandgap reference circuit with current mode structure. The designed CMOS bandgap voltage reference is in the range of -20°C to 100°C with temperature coefficient of 9.6 ppm/°C and provides a good Power Supply Rejection Ratio(PSRR) of 79dB in the low frequency. The results of simulation show that the design improve the performance of the bandgap reference voltage source effectively.

A novel bandgap reference (BGR) with low temperature and supply voltage sensitivity without any resistor, which is compatible with standard CMOS process, is presented in this article. The proposed BGR utilises a differential amplifier with an offset voltage proportional to absolute temperature to compensate the temperature drift of emitter–base voltage. Besides, a self-biased current source with feedback is used to provide the bias current of the BGR core for reducing current mirror errors dependent on supply voltage and temperature further. Verification results of the proposed BGR implemented with 0.35 µm CMOS process demonstrate that a temperature coefficient of 10.2 ppm/°C is realised with temperature ranging from −40°C to 140°C, and a power supply rejection ratio of 58 dB is achieved with a maximum supply current of 27 µA. The active area of the presented BGR is 160 × 140 µm2.

In order to meet the market demand for wide temperature range and high precision bandgap voltage reference, this paper designs a bandgap reference with wide temperature range and low temperature coefficient. In this paper, the basic implementation principle of the bandgap reference is analyzed.On the basis of the traditional bandgap reference circuit structure,this design adds a trimming network and a temperature compensation network. A new Gaussian bell curve compensation technique is adopted to compensate the low temperature section, and the normal temperature section and the high temperature section respectively. Compared with the existing compensation technology, the versatility and the compensation effect is better. The designed circuit is designed and manufactured based on the Huahong HHNECGE0.35um process. The results show that the output voltage is 2.5V at 2.7V supply voltage and temperature range of -40-125°C.at typical process angle ,the temperature coefficient is 0.54618 PPm/°C,and is within 1PPm/°C at other process angles.

Designing alloys with an accurate temperature-independent electrical response over a wide temperature range, specifically a low temperature coefficient of resistance (TCR), remains a big challenge from a material design point of view. More than a century after their discovery, Constantan (Cu-Ni) and Manganin (Cu-Mn-Ni) alloys remain the top choice for strain gauge applications and high-quality resistors up to 473-573 K. Here, an average TCR is demonstrated that is up to ≈800 times smaller in the temperature range 5-300 K and >800 times smaller than for any of these standard materials over a wide temperature range (5 K < T < 1200 K). This is achieved for selected compositions of Alx CoCrFeNi high-entropy alloys (HEAs), for which a strong correlation of the ultralow TCR is established with the underlying microstructure and its local composition. The exceptionally low electron-phonon coupling expected in these HEAs is crucial for developing novel devices, e.g., hot-electron detectors, high-Q resonant antennas, and materials in gravitational wave detectors.

Studies on use of lead iron tungstate-lead titanate relaxor binary system as a pressure sensing material

A high-order curvature-compensated CMOS bandgap reference (BGR) topology with a low temperature coefficient (TC) over a wide temperature range and a high power supply reject ratio (PSRR) is presented. High-order correction is realized by incorporating a nonlinear current INL, which is generated by ∆VGS across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μm 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of 0.19 ppm/°C over the temperature range of 165 °C (−40 to 125 °C), PSRR of −123 dB @ DC and −56 dB @ 100 kHz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V.

High linear voltage reference circuitry is designed and implemented in TSMC 0.13 mum and 0.18 mum CMOS technology. Previous research has proposed the use of MOS transistors operating in the weak inversion region to replace the bipolar devices in conventional PTAT (proportional to absolute temperature) circuits. However, such solutions often have linearity problem in high temperature region due to the current leaking devices in modern deep sub micron and nano-scale CMOS technology. The proposed circuit utilized temperature complementation technique on two voltage references, PTAT and IOAT (independent of absolute temperature) references, to enhance the linearity and produce a more stable lOAT voltage reference. Base on the simulation results, the R-squares of both circuitries are better than 0.999 in a considerable wider temperature range from -55degC to 170degC. Thus, a fully integrated temperature sensor with wider temperature range is designed and easily to integrate to modern system-on-chip designs with minimal efforts.

The MOSFET Zero Temperature Coefficient (ZTC) condition is a strategy that can be used to implement low temperature sensitivity circuits, such as current and voltage references. This condition is usually analyzed using the strong inversion quadratic MOSFET model. In this work we use a different approach, based on a continuous MOSFET model that can predict its behavior from weak to strong inversion. Based on this analysis, we verify that the ZTC point occurs from moderate to strong inversion for any CMOS process, since this point must occur for gate-source voltages larger than one threshold voltage. Also, a resistorless switched capacitor current reference based on the ZTC condition (ZSCCR), presenting low temperature coefficient (TC), is presented. The ZSCCR is designed in a 180 nm process, resulting a reference current of 5.88 µA under a supply voltage of 1.8 V, and occuping a silicon area around 0.010mm2. Results from circuit simulation show an effective temperature coefficient (TC eff ) of 60 ppm/°C from −45 to +85 °C and a power consumption of 63 µW.

This brief proposes a nano-watt self-biased CMOS voltage reference (SBCVR) with a quasi self-cascode current mirror (QSCCM) for better line sensitivity (LS) and power supply rejection ratio (PSRR). A self-cascode MOSFET (SCM) and a cascode structure are combined as the QSCCM to reduce the variations of bias current <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(I_{\mathrm{ B}})$ </tex-math></inline-formula> through the QSCCM, comparing to conventional ones. Then, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{ B}}$ </tex-math></inline-formula> is fed into an active load to acquire a more stable reference voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(V_{\mathrm{ REF}})$ </tex-math></inline-formula> against the supply voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(V_{\mathrm{ DD}})$ </tex-math></inline-formula> without using any additional native devices, amplifiers, pre-regulation circuits, and DIBL compensation circuits. The proposed SBCVR with the QSCCM is fabricated in a standard <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18 \mu \text{m}$ </tex-math></inline-formula> CMOS process, while 22 chip samples are measured. The results show that the average LS is 0.011%/V when the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ DD}}$ </tex-math></inline-formula> varies from 0.8 V to 1.8 V. The average PSRR are −76dB, −53 dB, and −59 dB at 10Hz, 1kHz, and 1MHz respectively. Moreover, it can produce a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ REF}}$ </tex-math></inline-formula> of 293 mV and consume a supply current of 1.95 nA <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(V_{\mathrm{ DD}}=$ </tex-math></inline-formula> 1V) at 27 °C. The average temperature coefficient (TC) is 66.1 ppm/°C without trimming in the temperature range from −40 °C to 85 °C, while the total area is only 0.004 mm 2.

This paper proposes a low bandgap reference voltage circuit with low temperature coefficient and independent of suply voltage for applications to power management IC. This proposed circuit is design and implemented using the TSMC 0.35μm CMOS 2P4M process. Based on simulated and measured results , the chip size is 20.6000.680mm with power dissipation about 3.3mW, and the operation temperature range form 0Cto 100C with temperature coefficient about 9.29/ppmC. The chip suply voltage can from 2.9V to 3.3V with PSRR about 44.2 dB, and its output reference voltage can stable at 0.65V.

The time needed to produce a regular action by the various drugs (digitalis, strophanthine, strychnine, picrotoxin, guanidine, chloral hydrate and urethane) was measured at intervals of 5°C at the temperature of 10°C to 30°C or 35°C. In this case the dosage of each drug was changed at each temperture over a wide range, and thus temperature coefficient at each range of temperature was calculated. The results are as follows : (1) Between 15°C and 30°C temperature coefficient was not remarkably different in any drugs, increased in proportion to increase of dosage of drugs and its value was about 2. (2) In the experimental examples at 30°C to 35°C the value ot temperature coefficient (Q10) was fairly large in picrotoxin and strophanthine and on the contrary Q10 was small in urethane. At the low temperature of 10°C to 15°C Q15 became abruptly large but became reversely small in urethane. So the changing point seemed to be in the range of the above temperature. This changing point in strophanthine was about 13°C. (3) In the experiment which the surrounding temperature was artificially changed Q10 coincided with the above results. Therefore increase or decrease of the time needed to produce the action by the seasonal change seems chiefly to be due simply to the difference of the surrounding temperature. (4) The little difference of temperature coefficient among each drug should prove that the chemical change of drugs themselves or the direct participation of drugs to cellular metabolism must not be the essential quality of action of drugs. The reason which Van't Hoff's law can be applied to action of drugs may be thought that the rate of adsorption of drugs into the active point of cells is under the influence of temperature. (5) Temperature coefficient of action of drugs injected subcutaneously takes the genuine value near by the minimum effective dosage. When the time needed to the gradual increase of concentration in blood in proportion to the increase of dosage of drugs is permitted, temperature coefficient takes the larger value than the genuine one, and the process which drugs are absorbed into the blood vessel through the part injected subcutaneously does not give an influence to temperature coefficient, because in this case there may be not adsorption. (6) When the relation between the minimum effective dosage of each drug and temperature at 15°C aud 25°C was investigated, it was found that the minimum effective dosage hardly changed by the difference of temperature but had possibility to become slightly small at high temperature. (7) After all temperature coefficient of action of drugs is not nearly estimated from the active dosage, but is determined by the comparison of the time needed to produce the action of a certain dosage of drugs.

A method for designing high precision bandgap voltage references which expresses the zero-Kelvin bandgap voltage of silicon (V GO ), a physical temperature-independent constant, at the output over a wide temperature range is proposed. In contrast to existing approaches that provide curvature compensation to reduce nonlinear temperature dependence, the proposed bootstrapping approach ideally cancels all temperature nonlinearities. Following this approach, a high precision voltage reference circuit which expresses the bandgap voltage of silicon at its output has been designed in a UMC 65nm process. Transistor-level Spectre simulations predict an output of approximately 1.18V and a temperature coefficient of 0.7ppm/°C from -40 °C to 125 °C. The method is partially verified with measurement results obtained by using diode-connected substrate pnp transistors fabricated in a UMC 65nm process along with discrete operational amplifiers to obtain a reference output with a temperature coefficient of 0.8ppm/°C over a 165°C temperature range.